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01/2013;
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D. Pawlik,
B. Romanczyk,
P. Thomas,
S. Rommel,
M. Edirisooriya,
R. Contreras-Guerrero,
R. Droopad,
W-Y Loh,
M.H.Wong,
K. Majumdar,
W.-E Wang,
P.D. Kirsch, R. Jammy
International Electron Device Meeting, San Francisco, CA USA; 12/2012
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Y T Chen,
J Huang,
J Price,
P Lysaght,
D Veksler,
C Weiland,
J C Woicik,
G Bersuker,
R Hill,
J Oh,
P D Kirsch, R Jammy,
J C Lee
Proceedings of the 2012 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA). 01/2012;
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physica status solidi (a). 01/2012;
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Applied Physics Letters 01/2012; 100(12):123502-123502. · 3.84 Impact Factor
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VLSI Technology, Systems, and Applications (VLSI-TSA), 2012 International Symposium on; 01/2012
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Se-Hoon Lee,
P. Majhi,
D.A. Ferrer,
Pui-Yee Hung,
J. Huang,
J. Oh,
Wei-Yip Loh,
B. Sassman,
Byoung-Gi Min,
Hsing-Huang Tseng,
R. Harris,
G. Bersuker,
P.D. Kirsch, R. Jammy,
S.K. Banerjee
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ABSTRACT: Preserving the integrity (e.g., Ge concentration, strain, and lattice perfection) of pseudomorphically grown silicon germanium (SiGe) heterostructure channels on Si substrates is one of the most critical factors in obtaining optimal pMOSFET performance from high hole mobility of strained SiGe. A millisecond Flash-assisted rapid thermal annealing (RTA) technique was applied to source/drain (S/D) dopant activation of high-Ge-concentration SiGe channel MOSFETs with a high- k /metal gate stack. Flash annealing of SiGe channel pMOSFETs is shown to be an effective way to preserve channel integrity while achieving a low S/D resistance. Excellent mobility and short-channel device performance are realized. In addition, as the concentration of Ge in the SiGe layer is increased, high B activation can be achieved with a lower peak temperature Flash anneal. As a result, the sheet resistance of the implanted p<sup>+</sup> junction can be comparable with that of higher temperature Flash-annealed (or optimal spike-annealed) Si. Furthermore, minimizing Ge diffusion reduces performance variation (such as statistical threshold voltage variation), which may be caused by the introduction and/or growth of defects in the strained SiGe heterostructure channel. It is shown that high-performance SiGe channel pMOSFETs with high Ge concentrations and a scaled high- k /metal gate can be achieved by a millisecond Flash-assisted RTA technique while preventing undesirable effects in the SiGe channel, such as within-wafer statistical performance variation.
IEEE Transactions on Electron Devices 10/2011; · 2.32 Impact Factor
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Hyuk-Min Kwon,
In-Shik Han,
Jung-Deuk Bok,
Sang-Uk Park,
Yi-Jung Jung,
Ga-Won Lee,
Yi-Sun Chung,
Jung-Hwan Lee,
Chang Yong Kang,
P. Kirsch, R. Jammy,
Hi-Deok Lee
[show abstract]
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ABSTRACT: The behavior of I<sub>D</sub> random telegraph signal (RTS) noise of a p-MOSFET with an advanced gate stack of HfO<sub>2</sub>/TaN is experimentally investigated and discussed. The I<sub>D</sub>-RTS noise is evaluated on a wafer level (100 sites) for statistical evaluation. The observed ratio of I<sub>D</sub>-RTS noise on a wafer is quite similar to that of a p-MOSFET with the conventional plasma-SiON dielectric, which means that the noise distribution on a wafer level is independent of the gate oxide structure and/or material. However, the relative magnitude of change of the drain current to the applied current (ΔI<sub>D</sub>/I<sub>D</sub>) of the p-MOSFETs with high-k (HK) dielectrics is greater than that of p-MOSFETs with conventional plasma-SiON dielectrics by about six times due to the greater number of preexisting bulk traps in the HK dielectric. Therefore, I<sub>D</sub>-RTS noise and its associated 1/f noise can present a serious issue to the CMOSFET with an advanced HK dielectric for low-power analog and mixed-signal applications.
IEEE Electron Device Letters 06/2011; · 2.85 Impact Factor
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ABSTRACT: pMOSFET performance of high Ge content (~50%) biaxial compressive strained SiGe heterostructure channel pMOSFETs is characterized, and performance between 〈110 〉 and 〈100 〉 channel orientations on a (001) substrate is compared for physical channel lengths down to ~80 nm. Temperature-dependent mobility and velocity are characterized for both channel directions. First, it is shown that high Ge content SiGe-based channels can deliver drive current enhancement over unstrained Si below sub-100-nm channel lengths. Second, it is found that, with a higher Ge content SiGe channel under biaxial compressive strain, there is a difference of drive current between 〈110 〉 and 〈100 〉 channel directions, and the difference increases when temperature is lowered and/or when channel length is scaled down. An external series resistance difference is detected between two channel directions, although it appears to be insufficient to explain all the direction-dependent drive current difference. Channel transport behavior in different channel orientations can be clearly observed with low external source/drain (S/D) series resistance achieved with a millisecond S/D dopant activation anneal process while controlling the thermal budget. Two possibilities have been investigated to understand channel-direction-dependent performance: possible differences in effects of device processing impact between two channel directions and anisotropic transport effects from an anisotropic hole band structure, particularly under biaxial compressive strain in a SiGe channel pseudomorphically grown on a Si substrate.
IEEE Transactions on Electron Devices 05/2011; · 2.32 Impact Factor
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ABSTRACT: In this letter, we analyze the nonsaturating upturns of capacitance under strong accumulation bias in MOS capacitors with high-k dielectrics. By comparing the electrical properties of dielectric samples with and without HfO<sub>2</sub> and by varying the ambient temperature, it is found that the conduction through the shallow trap levels in the HfO<sub>2</sub> bulk produces not only a steady-state current but also a dynamic current, which, in turn, causes the upturn in capacitance. The addition of RC shunts to the conventional small-signal model is proposed to consider the dynamic leakage effect. The model's effectiveness is verified by fitting the measured impedance spectrum and the measured capacitance. We suggest that measuring at a high frequency of hundreds of megahertz eliminates the dynamic interaction by shallow trap levels, allowing gate capacitance to be successfully reconstructed.
IEEE Electron Device Letters 05/2011; · 2.85 Impact Factor
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ABSTRACT: In this letter, we show an improvement not only in performance but also in reliability of a 30-nm-thick biaxially strained SiGe (20% Ge) channel on Si p-type metal-oxide semiconductor field-effect transistors. Compared with a Si chan nel, a strained SiGe channel allows larger hole mobility μ<sub>h</sub> in the transport direction and alleviates charge flow toward the gate oxide. μ<sub>h</sub> enhancement by 40% in SiGe and 100% in Si-cap/SiGe is observed compared with Si hole universal mobility. A ~40% reduction in negative-bias temperature instability degradation, gate leakage, and flicker noise is observed, which is attributed to a 4% increase in the hole-oxide barrier height φ in SiGe. A similar field acceleration factor Γ for the threshold voltage shift Δ<sub>VG</sub> and an increase in noise ΔS<sub>VG</sub> m Si and SiGe suggest identical degradation mechanisms.
IEEE Electron Device Letters 04/2011; · 2.85 Impact Factor
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Chenming Hu,
P. Patel,
A. Bowonder,
Kanghoon Jeon,
Sung Hwan Kim,
Wei Yip Loh,
Chang Yong Kang,
Jungwoo Oh,
P. Majhi,
A. Javey,
Tsu-Jae King Liu, R. Jammy
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ABSTRACT: Well designed tunneling green transistor may enable future VLSIs operating at 0.1V. Sub-60mV/decade characteristics have been convincingly demonstrated on 8" wafers. Large I<sub>ON</sub> at low V<sub>DD</sub> are possible according to TCAD simulations but awaits verification. V<sub>DD</sub> scaling will greatly benefit from low (effective) band gap energy, which may be provided by type II heterojunctions of Si/Ge or compound semiconductors.
Electron Devices Meeting (IEDM), 2010 IEEE International; 01/2011
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ABSTRACT: We demonstrate for the first time contact resistance reduction using dielectric dipole mitigated Schottky barrier height (SBH) tuning on a FinFET source/drain. Different techniques for forming a SiO<sub>2</sub>/AlO<sub>x</sub> dipole layer are investigated using diodes. FinFETs, with contacts containing a SBH tuning dipole layer, are also presented. Reduction of the SBH by 100meV from the AlO<sub>x</sub>/SiO<sub>2</sub> dipole results in a 10Ω-μm<sup>2</sup> reduction in specific contact resistivity (ρ<sub>CO</sub>) and a 100Ω-μm reduction in FinFET source/drain resistance (R<sub>S/D</sub>). Larger reductions of ρ<sub>CO</sub> should be possible if chemically formed or atomic-layer deposited SiO<sub>2</sub> is used in the dipole layer instead of interfacial SiO<sub>2</sub> due to the larger SBH reduction (ΔSBH ~300meV) obtained from these oxidation methods. Contact formation without the need for silicide makes this technique very promising for emerging devices, alternative channel materials, and sub-22nm CMOSFETS.
Electron Devices Meeting (IEDM), 2010 IEEE International; 01/2011
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G. Bersuker,
J. Yum,
L. Vandelli,
A. Padovani,
L. Larcher,
V. Iglesias,
M. Porti,
M. Nafría,
K. McKenna,
A. Shluger,
P. Kirsch, R. Jammy
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ABSTRACT: The evolution over time of the leakage current in HfO2-based MIM capacitors under continuous or periodic constant voltage stress (CVS) was studied for a range of stress voltages and temperatures. The data were analyzed based on the results of conductive atomic force microscopy (AFM) measurements demonstrating preferential current flow along grain boundaries (GBs) in the HfO2 dielectric and ab initio calculations, which show the formation of a conductive sub-band due to the precipitation of oxygen vacancies at the GBs. The simulations using the statistical multi-phonon trap-assisted tunneling (TAT) current description successfully reproduced the experimental leakage current stress time dependency by using the calculated energy characteristics of the O-vacancies. The proposed model suggests that the observed reversible increase in the stress current is caused by segregation of the oxygen vacancies at the GBs and their conversion to the TAT-active charge state caused by reversible electron trapping during CVS.
Solid-State Electronics 01/2011; 65-66:146. · 1.40 Impact Factor
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Junction Technology (IWJT), 2011 11th International Workshop on; 01/2011
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Semiconductor Device Research Symposium (ISDRS), 2011 International; 01/2011
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Electron Devices Meeting (IEDM), 2011 IEEE International; 01/2011
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ABSTRACT: Analyzed herein is the effect of different germanium (Ge) concentrations on negative bias temperature instability (NBTI) and channel hot carrier (CHC) degradations in high-performance Si<sub>1</sub><sub>-</sub><sub>x</sub>Ge<sub>x</sub> pMOSFETs. It is shown that higher concentrations result in less NBTI degradation due to the increased barrier height between the SiGe and high- k dielectric interface, but it causes greater CHC degradation due to the decreased channel bandgap with higher Ge concentrations. Therefore, the tradeoff between NBTI and HC degradations for different Ge concentrations should be considered when developing high-performance Si<sub>1</sub><sub>-</sub><sub>x</sub>Ge<sub>x</sub> pMOSFETs.
IEEE Electron Device Letters 12/2010; · 2.85 Impact Factor
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Min Sang Park,
Kyong Taek Lee,
Chang Yong Kang,
Gil-Bok Choi,
Hyun Chul Sagong,
Chang Woo Sohn,
Byoung-Gi Min,
Jungwoo Oh,
P. Majhi,
Hsing-Huang Tseng,
J.C. Lee,
Jeong-Soo Lee, R. Jammy,
Yoon-Ha Jeong
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ABSTRACT: We present a comparative study of the effects of a Si capping layer on SiGe channel pMOSFETs used for radio-frequency (RF) applications. In Si-capped devices, the drive current increases because Si/SiGe heterojunction layers form a SiGe quantum well, which reduces carrier scattering. Conversely, SiGe samples without a Si capping layer suffer severe interface degradation, due to Ge diffusing into the gate dielectric. Devices using a Si capping layer have enhanced RF performance and reduced low-frequency noise, which is a key factor affecting phase noise. There is an increase in the RF figures of merit. These benefits indicate that a Si capping layer should be used in SiGe channel pMOSFETs.
IEEE Electron Device Letters 11/2010; · 2.85 Impact Factor
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ABSTRACT: The time evolution of the leakage current in HfO<sub>2</sub> based MIM capacitors under constant voltage stress applied either continuously or with periodic interruptions was studied for a range of stress voltages and temperatures. The data analysis was performed based on the results of the conductive AFM measurements demonstrating preferential current flow along grain boundaries (GB) in the HfO<sub>2</sub> dielectric and ab initio calculations, which show the formation of a conductive sub-band due to oxygen vacancy precipitation at GBs. The proposed model suggests that the observed reversible increase in leakage current is caused by the defects segregation at GBs and electron trapping/detrapping at these defects. The energy characteristics of the electrically active defects extracted from the electrical measurements match well with those calculated for neutral oxygen vacancies in hafnia.
Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European; 10/2010
