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ABSTRACT: This paper presents an extension of the ANC ("Analogue Network of Converters")-based method, which is an original Design-for-Test (DfT) technique associated to a dedicated test algorithm to characterize the harmonic components of a set of embedded converters using only digital test resources. The ANC-based method was primarily developed under the assumption that the harmonics' phase is proportional to the input phase. This assumption is not valid for all converter architectures, where filtering effects may affect the harmonics' phase. The improved ANC-based method is able to calculate the magnitude of the harmonic components with unknown phase. The fundamental principle of this improved version of the ANC-based method is the same, but further mathematical developments have been established using a model independent from the harmonics' phase. The simulation results and the experiments show an excellent agreement between the values measured using the method and the values measured with a usual test setup, for the THD and SFDR parameters. Simulations were carried out considering both random phases and realistic phase delays such as the ones induced by a low pass filter.
Journal of Electronic Testing Theory and Applications. 01/2011; 27(3):335-350.
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ABSTRACT: In this paper, we present an extension of the ANC (“Analogue Network of Converters”)-based method to characterize the harmonic components of a set of converters with random-phase harmonics using only digital test resources. The ANC-based method was primarily developed under the assumption that the harmonics' phase is proportional to the input phase. This assumption is not valid for all converter architectures, where filtering effects may affect the harmonics' phase. The improved ANC-based method is able to calculate the magnitude of the harmonic components regardless of their phase. The simulation results and the experiments show an excellent agreement between the values measured using the method and the values measured with a usual test setup, for the THD and SFDR parameters.
Mixed-Signals, Sensors and Systems Test Workshop (IMS3TW), 2010 IEEE 16th International; 07/2010
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ABSTRACT: This paper presents a new technique called ldquoAnalog Network of Convertersrdquo that allows to test a set of ADCs and DACs embedded in a complex circuit as SiP and SoC. It presents an experimental validation of this new concept that permits to reduce drastically the testing time and requires only a low cost digital ATE.
Circuit Theory and Design, 2009. ECCTD 2009. European Conference on; 09/2009
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ABSTRACT: Standard production test techniques for ADC require an ATE with an arbitrary waveform generator (AWG) with a resolution at least 2 bits higher than the ADC under test resolution. This requirement is a real issue for the new high-performance ADCs. This paper proposes a test solution that relaxes this constraint. The technique allows the test of ADC harmonic distortions using only low-cost ATE. The method involves two steps. The first step, called the learning phase, consists in extracting the harmonic contributions from the AWG. These characteristics are then used during the second step, called the production test, to discriminate the harmonic distortions induced by the ADC under test from the ones created by the generator. Hardware experimentations are presented to validate the proposed approach.
VLSI Design 01/2008; 2008(2):17.
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ABSTRACT: System-in-Package (SiP) has recently become a significant technology in the semiconductor industry, offering to the consumer applications many new product features without increasing the overall form factor. In this talk, the basic SiP concepts are first discussed, showing difference between SiP and SoC, illustrated by some examples, drawn from real-life cases. The specific challenges are considered from the testing point of view, focussing on the assembled yield and defect level for the packaged SiP. Various bare-die test techniques to find known-good-dies are described including their limitations, followed by two techniques to test the SiP at the system level: functional system test and embedded component test. A brief discussion on future SiP design and test challenges concludes the presentation.
European Test Symposium, 2007. ETS '07. 12th IEEE; 06/2007
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ABSTRACT: In this paper, complex mixed signal circuits such as SiP or SOC including several ADCs and DACs are considered. A new DFT technique is proposed allowing the test of this complete set of embedded ADCs and DACs in a fully digital way such that only a simple low cost tester can be used. Moreover, this technique called "analogue network of converters " (ANC) requires an extremely simple additional circuitry and interconnect.
Test Symposium, 2007. ETS '07. 12th IEEE European; 06/2007
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ABSTRACT: The trend towards highly-integrated electronic devices has lead to a growth of system-in-package and system-on-chip technologies, where data converters play a major role in the interface between the real analogue world and digital processing. Testing these converters with accuracy and at low cost represents a big challenge because the observability and controllability of these blocks is reduced and the test operation requires a lot of time and expensive analogue instruments. A new design-for-test technique called `analogue network of converters' is presented. This technique aims at testing a set of analogue-to-digital converters and digital-to-analogue converters in a fully digital setup (using a low-cost digital tester). The proposed method relies on a novel processing of the harmonic distortion generated by the converters and requires an extremely simple additional circuitry and interconnects
IET Computers & Digital Techniques 06/2007; · 0.45 Impact Factor
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ABSTRACT: Integral non-linearity (INL) is the main static parameter of analog-to-digital converter. This paper presents a comparison
between different INL test techniques based on INL estimation from the spectrum of the converted signal. The most common technique
is based on polynomial fitting of the INL curve. This technique is well suited to the estimation of a smooth INL curve without
sharp transitions. The new method described in the paper is based on a Fourier series expansion of the INL curve. We demonstrate
that this new technique allows a more efficient INL estimation. The comparison between the two techniques has been realized
thanks to a metrics that considers the uncertainty of production test measurements. Finally, we propose a first step of the
study of implementation feasibility of the INL estimation technique. This study focus only on the optimization of required
memory.
Journal of Electronic Testing 11/2006; 22(4):351-357. · 0.47 Impact Factor
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ABSTRACT: The paper shows a new concept for testing a system-in-package (SiP) using a wireless communication. Trends of the SiP technology put more economic and technical constraints onto the test, while the contactless test techniques represent an opportunity to overcome the inherent problems. In this paper, we introduce a new test concept based on a wireless communication, a specific test access mechanism (TAM), and an optimised architecture. Although this approach is dedicated to an intermediate test of SiP, we explore other potential applications of this technology
Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. International Conference on; 10/2006
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ABSTRACT: Testing mixed-signal circuits remains one of the most difficult challenges within the semiconductor industry. In this article, the authors present a novel DFT technique to test sets of ADCs and DACs embedded in a complex SiP. The technique provides fully digital testing on the converters to significantly reduce the cost of testing
IEEE Design and Test of Computers 06/2006; · 1.39 Impact Factor
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ABSTRACT: The Integral Non-Linearity (INL) is the most significant static parameter of Analog-to-Digital Converters. This paper presents a comparison between different INL test techniques based on INL estimation from the spectrum of the converted signal. Then, we investigate whether the most accurate technique is applicable in a realistic hardware configuration.
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ABSTRACT: This paper presents a technique allowing the test of ADC harmonic distortions with only low-cost ATE. Contrary to a classical DSP-based test that requires an arbitrary wave generator (AWG) on the ATE with a resolution at least 2 bit higher than the ADC under test, the proposed solution permits to test ADCs using same resolution AWG. The method involves an initial learning phase in which the characteristics of the AWG are extracted. These characteristics are then used during production test to discriminate the harmonic distortions induced by the ADC under test from the ones induced by the generator. Hardware experimentations are presented to validate the proposed approach.
