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ABSTRACT: A mixed-mode 3-D simulation study has been performed for ring oscillators made of 30-nm planar CMOS transistors with nonrectangular channel shapes. Nonrectangular shapes happen unintentionally due to optical proximity effects and can also be introduced intentionally. Transistors with large drains are shown to degrade ring-oscillator performance, whereas transistors with large sources are shown to simultaneously increase the ring-oscillator frequency by 25% and reduce the leakage current by a factor of three.
IEEE Electron Device Letters 02/2010; · 2.85 Impact Factor
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ABSTRACT: For 65nm and beyond process technologies, identical transistors within a die can show large variations in on-current characteristics for different layouts. The proximity to the transistor of edges associated with different mask levels contribute to variability. Lithography proximity effects are dominant but other physical phenomena encountered with various process steps such as ion scattering, transient enhanced diffusion (TED) and mechanical strain engineering contribute to the variability. These effects can be modeled with TCAD. The results can be incorporated into the current SPICE models to enable designers to do more accurate simulations of the circuit on actual silicon
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on; 11/2006
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ABSTRACT: Sub-90 nm CMOS circuits contain a significant amount of mechanical stress in active silicon. This stress is generated by a variety of intentional and unintentional stress sources. Shallow trench isolation is an example of an unintentional stress source, whereas embedded SiGe in the source and drain is an example of an intentional stress source. The amount of stress in each transistor in the circuit depends on the shape of its diffusion area as well as the density of the adjacent layout. The resulting non-uniform stress distribution alters individual transistor performance and, ultimately, the behavior of the circuit. In this paper, several examples are used to illustrate this effect based on design rules for the 45 nm technology node. A number of alternative approaches are suggested for partially suppressing or completely eliminating the stress-induced performance variations.
Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on; 04/2006
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Xi-Wei Lin
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ABSTRACT: After a brief review of the current DFM solutions, this presentation focuses on three areas: a) TCAD based modeling that brings process parameters into spice models, enabling direct communication between manufacturing and design. b) Stress proximity effects which cause design variability and require better modeling. c) The complexity of interconnect variations in timing analysis
ASIC, 2005. ASICON 2005. 6th International Conference On; 11/2005
