J. Hauer

Publications (7)0 Total impact

• Conference Proceeding: Modeling and simulation of CMOS APS

  B. Blanco-Filgueira, P. Lopez, D. Cabello, J. Ernst, H. Neubauer, J. Hauer
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  ABSTRACT: This work studies the importance of the peripheral collection in the overall photoresponse in deep sub-micron CMOS 3T active pixel sensors (APS), focusing on the contribution of the bottom surface of the depletion region. We analyze a semi-analytical expression, inspired by previous works, that models the photoresponse of a set of fabricated pixels with octagonal photodiodes that could be easily extended to different geometries. Device simulation results are used to study the behaviour of these structures with the purpose of using computer aided design (CAD) tools for the next technological nodes research.
  Electron Devices, 2009. CDE 2009. Spanish Conference on; 03/2009
• Conference Proceeding: Bottom collection of photodiode-based CMOS APS

  B. Blanco-Filgueira, P. Lopez, D. Cabello, J. Ernst, H. Neubauer, J. Hauer
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  ABSTRACT: The market for solid-state image sensors has been experiencing an explosive growth in recent years resulting in CMOS sensors rapidly becoming one of the emerging sectors with more projection potential in the semiconductors industry. A CMOS active pixel sensor (APS) with a reverse biased p-n junction photodiode constitutes the structure of more widespread use, and it has been made a viable alternative to CCDs with the advent of deep submicron CMOS technologies and microlenses. Peripheral area of the junction depletion region plays an important role on collecting photocarriers in the vicinity of photodiode limits. In this paper, the peripheral photoresponse of CMOS APS of different dimensions in a deep submicron 0.18iquestm process is studied, paying special attention to the bottom collection.
  Advanced Semiconductor Devices and Microsystems, 2008. ASDAM 2008. International Conference on; 11/2008
• Conference Proceeding: Performance analysis of high-speed MOS transistors with different layout styles

  P. Lopez, M. Oberst, H. Neubauer, J. Hauer, D. Cabello
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  ABSTRACT: Several layout schemes for MOS transistors have been investigated and compared in terms of speed and layout area. Among them, the so-called closed, donut or doughnut transistors have been characterized, obtaining an analytical expression for the calculation of the equivalent W/L ratio for a general n-side regular polygonal-shape. The comparisons show that with quasi-minimum dimension transistors and L=0.35 μm, reductions of up to 81% on the drain area can be achieved with an increase of only a 10% on the total layout area for given W and L. An application improving the switching speed of an output multiplexer is shown.
  Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on; 06/2005
• Conference Proceeding: Practical considerations on doughnut transistors design

  P. Lopez, M. Oberst, H. Neubauer, J. Hauer, D. Cabello
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  ABSTRACT: For applications where speed is important and custom design is an option, doughnut transistors constitute an attractive alternative to standard topologies, efficiently reducing parasitic capacitances while keeping large W/L ratios. This paper explores the influence of the layout style on the chip performance. To this aim a two-stage op-amp where different types of doughnut layouts have been considered for the Input differential pair has been constructed and measured. Experimental results suggest better performance for circle-type layouts.
  Circuit Theory and Design, 2005. Proceedings of the 2005 European Conference on;
• Article: Experimental analysis of CMOS short-channel gate enclosed transistors

  P. Lopez, B. Blanco-Filgueira, D. Cabello, J. Hauer
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  ABSTRACT: The outstanding benefits of standard deep submicron CMOS technologies for the design of radiation tolerant devices can be further exploited by means of the use of special layout styles, such as the gate-enclosed transistors. This work constitutes a study of the impact of technology downscaling on the performance of this type of devices, particularly the threshold voltage roll-off due to short-channel effects and the drain-induced barrier lowering. Theoretical predictions have been validated with experimental data in a commercial 0.18μm CMOS process.
  Fraunhofer IIS.
• Article: A study of CMOS radiation tolerant transistors using green functions

  P. Lopez-Martinez, D. Cabello, J. Hauer, B. Blanco-Filgueira
  Fraunhofer IIS.
• Article: A 2D model for radiation-hard CMOS annular transistors

  P. Lopez, B. Blanco-Filgueira, F. Pardo, D. Cabello, J. Hauer
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  ABSTRACT: Scaling benefits of CMOS processes include the reduction of the oxide thickness, which in turn favors the reduction of threshold voltage shifts due to radiation-induced gate oxide trapped charge. Moreover, experimental results have shown that this inherent radiation hardness of deep submicron processes can be further exploited using gate-enclosed layout transistors with an annular design. For an in-depth analysis of such structures, we present in this paper a 2D analytical I-V model for short-channel annular devices based on the direct solution of the Poisson equation in cylindrical coordinates. The theoretical approach is confirmed with experimental data in a standard CMOS 0.18 mu m process.
  Fraunhofer IIS.