C.X. Li

The University of Hong Kong, Hong Kong, Hong Kong

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Publications (37)50.09 Total impact

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    ABSTRACT: TaON is in situ formed as a passivating interlayer in Ge metal-oxide-semiconductor (MOS) capacitors with high-k TaTiO gate dielectric fabricated simply by alternate sputtering of Ta and Ti. Also, postdeposition annealing is performed in wet N <sub>2</sub> to suppress the growth of unstable GeO <sub> x </sub> at the Ge surface. As a result, excellent electrical properties of the Ge MOS devices are demonstrated, such as high equivalent dielectric constant (22.1), low interface-state density (7.3×10<sup>11</sup> cm <sup>-2</sup>  eV ) , small gate leakage current ( 8.6×10<sup>-4</sup> A   cm <sup>-2</sup> at V <sub> g </sub>- V <sub> fb </sub>=1 V ), and high device reliability. Transmission electron microscopy and x-ray photoelectron spectroscopy support that all these should be attributed to the fact that the nitrogen barrier in the TaON interlayer can effectively block the interdiffusions of Ge and Ta, and the wet- N <sub>2</sub> anneal can significantly suppress the growth of unstable low-k GeO <sub> x </sub> .
    Applied Physics Letters 06/2011; · 3.52 Impact Factor
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    ABSTRACT: Ge MOS capacitors with tri-layer gate dielectric are proposed by using GeON interlayer, TaON sandwich layer, and HfTiON high-k dielectric. Very small capacitance equivalent thickness (0.79~0.91 nm) is achieved. Experimental results show that the NO pretreated sample exhibits the best electrical properties, such as low interface-state density (5.4 × 10<sup>11</sup> cm<sup>-2</sup> eV<sup>-1</sup>), low gate leakage current density (~ 3.16 × 10<sup>-4</sup> Acm<sup>-2</sup> at V<sub>g</sub> - V<sub>fb</sub> = 1 V) and high device reliability. All of these should be attributed to the facts that the NO nitridation could form a GeON interlayer with suitable N content and thus provide an excellent GeON/Ge interface with strong Ge-N bonds, while the TaON sandwich layer could separate Hf and Ge, thus effectively preventing the reaction between them and improving the interface quality and electrical properties of the devices.
    IEEE Electron Device Letters 03/2011; · 2.79 Impact Factor
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    ABSTRACT: We developed Pt/tantalum oxide (Ta2O5) Schottky diodes for hydrogen sensing applications. Thin layer (4 nm) of Ta2O5 was deposited on silicon (Si) and silicon carbide (SiC) substrates using the radio frequency sputtering technique. We compared the performance of these sensors at different temperatures of 100 °C and 150 °C. At these operating temperatures, the sensor based on SiC exhibited a larger sensitivity, whilst the sensor based on Si exhibited a faster response toward hydrogen gas. We discussed herein, the experimental results obtained for these Pt/Ta2O5 based Schottky diodes exhibited that they are promising candidates for hydrogen sensing applications.
    Sensors and Actuators A Physical 01/2011; 172(1):9-14. · 1.84 Impact Factor
  • H.X. Xu, J.P. Xu, C.X. Li, P.T. Lai
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    ABSTRACT: Ge metal-oxide-semiconductor capacitors with La2O3 as gate dielectric are fabricated by e-beam evaporation of La2O3 followed by post-deposition annealing in different gases (NH3, N2, NO, N2O and O2). Experimental results indicate that the NH3, NO, N2O and O2 anneals give higher interface-state and oxide-charge densities, and thus larger gate leakage current, with the highest for the O2 anneal due to the growth of an unstable GeOx interlayer. On the other hand, the NH3 annealing improves the k value of the dielectric, while the annealings in O2-containing ambients (NO, N2O and O2) lead to the formation of a low-k GeOx interlayer, thus decreasing the equivalent k value. Compared with the above four samples, the sample annealed in N2 exhibits not only larger k value (18.3) and smaller capacitance equivalent thickness (2.14 nm), but also lower leakage current density (~ 10−3 Acm− 2 at Vg = 1 V) and smaller interface-state density (4.5 × 1011 eV− 1 cm− 2).
    Thin Solid Films 09/2010; 518(23):6962–6965. · 1.87 Impact Factor
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    ABSTRACT: The electrical properties of n-Ge metal-oxide-semiconductor (MOS) capacitors with HfO2/LaON or HfO2/La2O3 stacked gate dielectric (LaON or La2O3 as interlayer) are investigated. It is found that better electrical performances, including lower interface-state density, smaller gate leakage current, smaller capacitance equivalent thickness, larger k value, and negligible C-V frequency dispersion, can be achieved for the MOS device with LaON interlayer. The involved mechanism lies in that the LaON interlayer can effectively block the interdiffusions of Ge, O, and Hf, thus suppressing the growth of unstable GeOx interlayer and improving the dielectric/Ge interface quality.
    Applied Physics Letters 07/2010; 97(2):022903-022903-3. · 3.52 Impact Factor
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    ABSTRACT: Thin LaTiON gate dielectric is deposited on Ge (100) substrate by reactive co-sputtering of La<sub>2</sub>O<sub>3</sub> and Ti targets under different Ar/N<sub>2</sub> ratios of 24/3, 24/6, 24/12, and 24/18, and their electrical properties are investigated and compared. Results show that the LaTiON gate-dielectric Ge MOS capacitor prepared at an Ar/N<sub>2</sub> ratio of 24/6 exhibits highest relative permittivity, smallest capacitance equivalent thickness, and best electrical characteristics, including low interface-state density, small C-V hysteresis and low gate leakage current. This is attributed to the fact that a suitable N content in LaTiON can effectively suppress the growth of low-k GeO<sub>x</sub> interfacial layer between LaTiON and Ge substrate.
    Electron Devices and Solid-State Circuits, 2009. EDSSC 2009. IEEE International Conference of; 01/2010
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    ABSTRACT: In this work, Al/HfTiON/n-Si capacitors with different sputtering and annealing temperatures are studied. Larger accumulation capacitance and flat-band voltage are observed for samples with higher sputtering or post-deposition annealing temperature. Gate conduction mechanisms are only affected by sputtering temperature slightly. The flat-band voltage shift and interface-state density at midgap under high-field gate injection and substrate injection are investigated, and the results imply electron detrapping in the gate dielectric.
    Electron Devices and Solid-State Circuits, 2009. EDSSC 2009. IEEE International Conference of; 01/2010
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    C.X. Li, H.X. Xu, J.P. Xu, P.T. Lai
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    ABSTRACT: In this work, Ge MOS capacitors with Y<sub>2</sub>O<sub>3</sub> gate dielectric were fabricated. The effects of annealing in N<sub>2</sub>, NH<sub>3</sub> O<sub>2</sub> or NO ambient were investigated. Experimental results demonstrated that the NO annealing could improve both electrical properties and reliability of Ge MOS devices with Y<sub>2</sub>O<sub>3</sub> dielectric. On the other hand, the NH<sub>3</sub> annealing resulted in H-related traps while the O<sub>2</sub> annealing suffered from extra GeO<sub>x</sub> growth, thus both degrading the performance of the devices.
    Electron Devices and Solid-State Circuits, 2009. EDSSC 2009. IEEE International Conference of; 01/2010
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    ABSTRACT: In this paper, a compact threshold-voltage model is developed for stack high-k gate-dielectric MOSFET with a thin interlayer. The simulated results are in good agreement with 2-D simulations. The influences of k value of the interlayer on threshold behaviors are investigated in detail. A low-k interlayer can effectively improve the threshold-voltage behaviors. Furthermore, the ratio of low-k interlayer EOT (equivalent oxide thickness) to high-k layer EOT is optimized by considering both threshold-voltage roll-off and gate leakage current.
    Electron Devices and Solid-State Circuits, 2009. EDSSC 2009. IEEE International Conference of; 01/2010
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    ABSTRACT: In this work, Ge p-MOS capacitors with HfTiON gate dielectric were fabricated by sputtering method. Pre-deposition fluorine plasma treatment and post-deposition fluorine plasma annealing were used to improve the electrical and reliability properties of Ge p-MOS capacitors. Experimental results showed that both methods could improve the interface quality with lower interface-state density, less frequency dispersion, and also enhance the reliability properties with smaller increases of oxide charge and gate leakage after high-field stressing. Compared with pre-deposition fluorine-plasma treatment, post-deposition fluorine plasma annealing achieved higher quality of high-k/Ge interface such as lower interface-state density, higher dielectric constant and lower stress-induced gate leakage current. By XPS and AFM analyses, the improvements should be due to the passivation effects of fluorine on oxygen vacancies, dangling bonds and the dielectric surface.
    Solid-State Electronics 01/2010; 54(7):675-679. · 1.48 Impact Factor
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    ABSTRACT: In this paper, we fabricated Pt/tantalum oxide (Ta2O5) Schottky diodes for hydrogen sensing applications. Thin (4 nm) layer of Ta2O5 was deposited on silicon (Si) and silicon carbide (SiC) substrates by radio frequency (RF) sputtering technique. We compared the performance of these sensors at different elevated temperatures of 100∘C and 150∘C. At these temperatures, the sensor based on SiC exhibited a larger sensitivity while the sensor based on Si exhibited a faster response toward hydrogen gas. We discussed herein, the responses exhibited by the Pt/Ta2O5 based Schottky diodes demonstrated a promising potential for hydrogen sensing applications.
    Procedia Engineering. 01/2010; 5:147-151.
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    ABSTRACT: In this paper, Si-MOS capacitors with HfTiO/SiON stack gate dielectric were fabricated by using Si-surface thermal passivation in NO and N2O ambients respectively and reactive co-sputtering technology. Results show that the sample pretreated in NO ambient has excellent interface properties, low gate leakage current density and high reliability. This is attributed to the formation of a SiON interlayer with suitable proportion of N and O, and N-barrier role of isolating Ti in HfTiO from Si of the substrate, thus effectively preventing the inter-diffusions of Ti and Si during post-deposition annealing.
    01/2010;
  • C. X. Li, P. T. Lai
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    ABSTRACT: High-k and wide-bandgap Y2O3 was proposed as an interlayer in n-Ge metal-oxide-semiconductor (MOS) capacitor with HfTiO gate dielectric for passivating its dielectric/Ge interface, and thus improving its electrical properties and high-field reliability. Results showed that as compared to the Ge MOS capacitor with HfTiO dielectric, the sample with HfTiO/Y2O3 dielectric had better electrical properties such as higher dielectric constant (k=24.4), lower interface-state density, and less frequency-dependent C-V dispersion, and also better reliability with less increases in gate leakage and interface states after high-field stressing. This should be attributed to the excellent interfacial quality of Y2O3/Ge with no appreciable growth of unstable GeOx at the interface as confirmed by transmission electron microscopy. Moreover, Y2O3 can also act as a barrier against the diffusions of Ge, Hf, and Ti, thus further improving the interface quality.
    Applied Physics Letters 07/2009; 95(2). · 3.52 Impact Factor
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    ABSTRACT: Annealing of high-permittivity HfTiO gate dielectric on Ge substrate in different gases (N2, NH3, NO and N2O) with or without water vapor is investigated. Analysis by transmission electron microscopy indicates that the four wet anneals can greatly suppress the growth of a GeOx interlayer at the dielectric/Ge interface, and thus decrease interface states, oxide charges and gate leakage current. Moreover, compared with the wet N2 anneal, the wet NH3, NO and N2O anneals decrease the equivalent permittivity of the gate dielectric due to the growth of a GeOxNy interlayer. Among the eight anneals, the wet N2 anneal produces the best dielectric performance with an equivalent relative permittivity of 35, capacitance equivalent thickness of 0.81 nm, interface-state density of 6.4 × 1011 eV− 1 cm− 2 and gate leakage current of 2.7 × 10− 4 A/cm2 at Vg = 1 V.
    Thin Solid Films 03/2009; 517(9):2892-2895. · 1.87 Impact Factor
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    ABSTRACT: Reactive cosputtering is employed to prepare high-permittivity HfTiO gate dielectric on n-Ge substrate. Effects of Ge-surface pretreatment on the interface and gate leakage properties of the dielectric are investigated. Excellent performances of Al/HfTiO/GeO x N y /n-Ge MOS capacitor with wet–NO surface pretreatment have been achieved with a interface-state density of 2.1×1011eV−1 cm−2, equivalent oxide charge of −7.67×1011cm−2 and gate leakage current density of 4.97×10−5A/cm2 at V g =1V.
    Applied Physics A 01/2009; 94(2):419-422. · 1.69 Impact Factor
  • C.X. Li, X. Zou, J.P. Xu, P.T. Lai
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    ABSTRACT: HfTiO/GeO<sub>x</sub>N<sub>y</sub> and HfTiOn/GeO<sub>x</sub>N<sub>y</sub> stack gate dielectric are prepared by using wet-NO or wet-N<sub>2</sub>O pretreatment on Ge substrate. Experimental results show that the wet NO pretreatment can lead to excellent interface properties, gate leakage properties and device reliability, especially for the HfTiON/GeO<sub>x</sub>N<sub>y</sub> dielectric. The involvement mechanisms lie in the roles of N in blocking oxygen diffusion and Ge out-diffusion and suitable N incorporation in the GeO<sub>x</sub>N<sub>y</sub> interlayer, which effectively suppress further growth of GeO<sub>x</sub>N<sub>y</sub> interlayer and the growth of unstable GeO<sub>x</sub> during subsequent processing.
    Electron Devices and Solid-State Circuits, 2008. EDSSC 2008. IEEE International Conference on; 01/2009
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    ABSTRACT: Si MOS capacitors with HfTa oxide and oxynitride as gate dielectric were fabricated. Moreover, AlO<sub>x</sub>N<sub>y</sub> or TaO<sub>x</sub>N<sub>y</sub> was used as the interlayer between HfTa oxynitride and Si substrate to improve the electrical quality of the capacitors. Experimental results showed that the HfTaO<sub>x</sub>N<sub>y</sub> capacitor with TaO<sub>x</sub>N<sub>y</sub> interlayer achieved better performance with larger capacitance and smaller leakage current than its counterpart with AlO<sub>x</sub>N<sub>y</sub> interlayer.
    Electron Devices and Solid-State Circuits, 2008. EDSSC 2008. IEEE International Conference on; 01/2009
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    ABSTRACT: HfTiON gate dielectric is fabricated by reactive co-sputtering method followed by annealing in N2 ambient. The effects of Ti content and annealing temperature on the performances of HfTiON gate-dielectric Si MOS devices are investigated. Experimental results indicate that gate capacitance is increased with increasing Ti content. However, when the Ti/Hf ratio exceeds ~1.75, increase of the gate capacitance becomes small. Surface roughness of the samples annealed at different temperatures is analyzed by AFM, and results show that high annealing temperature (e.g. 700°C for 30 s) can produce smooth surface, thus resulting in low gate leakage current.
    01/2009;
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    ABSTRACT: In this work, Ge p-MOS capacitors with HfTiON dielectric were fabricated. Fluorine was incorporated by post-deposition plasma annealing or pre-deposition plasma treatment. Experimental results showed that fluorine could result in lower interface-state density, smaller frequency dispersion and better high-field reliability, with the former method better than the latter.
    Microelectronic Engineering - MICROELECTRON ENG. 01/2009; 86(7):1596-1598.
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    ABSTRACT: The electrical characteristics of germanium p-metal-oxide-semiconductor (p-MOS) capacitor and p-MOS field-effect transistor (FET) with a stack gate dielectric of HfO<sub>2</sub>/TaO x N y are investigated. Experimental results show that MOS devices exhibit much lower gate leakage current than MOS devices with only HfO<sub>2</sub> as gate dielectric, good interface properties, good transistor characteristics, and about 1.7-fold hole-mobility enhancement as compared with conventional Si p-MOSFETs. These demonstrate that forming an ultrathin passivation layer of TaO x N y on germanium surface prior to deposition of high- k dielectrics can effectively suppress the growth of unstable GeO x , thus reducing interface states and increasing carrier mobility in the inversion channel of Ge-based transistors.
    IEEE Electron Device Letters 11/2008; · 2.79 Impact Factor