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ABSTRACT: Ad hoc networks are threatened by a wide variety of accidental and malicious faults. This fact limits the practical exploitation of ad hoc networks. In consequence, apart from enforcing the dependability and security aspects of these networks, the provision of approaches to evaluate their behaviour in the presence of faults and attacks is of paramount importance. Accordingly, analysing and determining which threats should be considered for the evaluation of each particular ad hoc network is an essential task for the definition of representative faultloads. Our previous work focused on evaluating the impact of black and grey hole attacks in real networks using attack injection. This paper enriches the faultload of our experimental platform with five new types of accidental and malicious faults. The goal is to provide the basis for guiding the selection of suitable faultloads when assessing the impact of different threats in different types of ad hoc networks, like wireless sensor networks (WSN) and mobile ad hoc networks (MANET), considering the importance of the applicative context in the interpretation of results.
Dependable Computing (LADC), 2011 5th Latin-American Symposium on; 05/2011
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ABSTRACT: Ad hoc networks constitute a quick and cheap alternative to provide communications when deploying a fixed infrastructure could result prohibitive in terms of either time or money. Although the unique properties of ad hoc networks make them very sensitive to malicious faults (attacks), most of current research has focused on improving their routing capabilities, thus widening their application domains, and very little attention has been devoted to their dependability. Accordingly, the confident use of this technology requires the development of new techniques and tools to assess the robustness of such networks in presence of attacks. This paper deals with this challenging goal by proposing an attack injection approach based on real ad hoc networks as experimental platform. Experiments show the feasibility of the proposed approach and identify a large number of possibilities to increase our knowledge on how real ad hoc networks behave in practice.
Dependable Computing, 2009. PRDC '09. 15th IEEE Pacific Rim International Symposium on; 12/2009
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ABSTRACT: Current practices for the design and deployment of hardware redundancy techniques in embedded systems remain in practice specific (defined on a case-per-case basis) and mostly manual. This paper addresses the challenging problems of engineering fault tolerance mechanisms in a generic way and providing suitable tools for coping with their deployment. This approach relies on metaprogramming to specify fault tolerance mechanisms and open compilers to automatically deploy such mechanisms on the selected hardware core. Our previous research has already shown the suitability of this approach for the generic design and automatic deployment of NMR strategies. In this paper, we explore the usefulness of the idea in the context of information redundancy. The main contribution is the development of a metaprogram for the provision of ECC-based fault tolerance in data storage elements (registers and memory modules). It is also shown to what extend such metaprogram can be useful for improving the reliability of communications between HW cores in embedded systems.
Emerging Technologies & Factory Automation, 2009. ETFA 2009. IEEE Conference on; 10/2009
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ABSTRACT: Many designers bet on reducing time-to-market costs by integrating off-the-shelf (OTS) cores in their embedded solutions, while looking after maintaining the confidence placed by users in their products. Balancing these aspects is challenging and claims for suitable techniques to select, among eligible candidates, those exhibiting adequate levels of dependability. Thus, the early and efficient dependability assessment of embedded cores is nowadays a major and complex challenge. This paper focuses on the assessment and comparison of dependability attributes evinced by hardware OTS cores. It proposes the use of field programmable gate arrays to emulate the cores behaviour under different execution profiles (workloads and faultloads). Three cores devoted to signal filtering purposes are considered as a case study. Results show not only the feasibility of this approach but also the kind of selection process supported by the proposed technique.
Dependable Computing Conference, 2008. EDCC 2008. Seventh European; 06/2008
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ABSTRACT: Advances in semiconductor technologies are greatly increasing the likelihood of fault occurrence in deep-submicrometer manufactured VLSI systems. The dependability assessment of VLSI critical systems is a hot topic that requires further research. Field-programmable gate arrays (FPGAs) have been recently pro posed as a means for speeding-up the fault injection process in VLSI systems models (fault emulation) and for reducing the cost of fixing any error due to their applicability in the first steps of the development cycle. However, only a reduced set of fault models, mainly stuck-at and bit-flip, have been considered in fault emulation approaches. This paper describes the procedures to inject a wide set of faults representative of deep-submicrometer technology, like stuck-at, bit-flip, pulse, indetermination, stuck-open, delay, short, open-line, and bridging, using the best suitable FPGA- based technique. This paper also sets some basic guidelines for comparing VLSI systems in terms of their availability and safety, which is mandatory in mission and safety critical application contexts. This represents a step forward in the dependability benchmarking of VLSI systems and towards the definition of a framework for their evaluation and comparison in terms of performance, power consumption, and dependability.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 05/2008; · 1.22 Impact Factor
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ABSTRACT: A confident use of deep-submicron VLSI systems requires the study of their behaviour in the presence of faults, which has been traditionally conducted via model-based fault injection techniques. Although field-programmable gate arrays (FPGAs) allows for a fast execution of models, its use to emulate the occurrence of permanent faults in VLSI models has been restricted so far to the well-known stuck-at fault model. Recent studies in fault representativeness point out the need of considering a wider set of faults modelling aspects like delays or short circuits. This paper presents new and different alternatives for the emulation of permanent faults. Several experiments have been performed using an automated tool that allows for the injection of all the studied fault models. Results from these experiments show both the feasibility of the proposed approach, and the time saving achieved by executing the models on FPGAs
Field Programmable Logic and Applications, 2006. FPL '06. International Conference on; 09/2006
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ABSTRACT: Advances in circuitry integration increase the probability of occurrence of transient faults in VLSI systems. A confident use of these systems requires the study of their behaviour in the presence of such faults. This study can be conducted using model-based fault injection techniques. In that context, field-programmable gate arrays (FPGAs) offer a great promise by enabling those techniques to execute models faster. This paper focuses on how run-time reconfiguration techniques can be used for emulating the occurrence of transient faults in VLSI models. Although the use of FPGAs for that purpose has been restricted so far to the well-known bit-flip fault model, recent studies in fault representativeness point out the need of considering a wider set of faults modelling aspects like delays, indeterminations and pulses. Therefore, the main goal of this study is to analyse the different alternatives that FPGAs offer for the emulation of these faults while greatly decreasing the time devoted to models execution
Dependable Systems and Networks, 2006. DSN 2006. International Conference on; 02/2006
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ABSTRACT: As manufacturers integrate more off-the-shelf components in embedded products, their robustness evaluation becomes more necessary. This requirement is however difficult to meet using non-intrusive evaluation methods, especially in the case of systems-on-a-chip (SoCs). Research presented in this paper investigates the use of on-chip-debugging (OCD) mechanisms to evaluate the ability of SoC-embedded software components to withstand the occurrence of external faults. These faults are emulated by corrupting the information that components are able to receive through their public interfaces. Once a fault has been injected, reaction of targeted components is studied using OCD monitoring capabilities. The ability of these capabilities to run in parallel with the rest of the SoC internal mechanisms is exploited in order to carry out previous tasks without requiring the source code of the component under study and without interfering (neither spatially nor temporally) with the system nominal execution. Results show potentials and limitations of the approach and let us define directions for future investigation.
Dependable Computing, 2005. Proceedings. 11th Pacific Rim International Symposium on; 01/2006
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ABSTRACT: The pervasive use of ECUs (electronic control units) in automotive systems motivates the interest of the community in methodologies for quantifying their dependability in a reproducible and cost-effective way. Although the core of modern vehicle engines is managed by the control software embedded in engine ECUs, no practical approach has been proposed so far to characterise the impact of faults on the behaviour of this software. This paper proposes a dependability benchmark for engine control applications. The essential features of such type of applications are first captured in a general model, which is then exploited in order to specify a standard procedure to assess dependability measures. These measures are defined taking into account the expectations of industrials purchasing engine ECUs with integration purposes. The benchmark also considers the current set of technological limitations that the manufacturing of modern engine ECUs imposes to the experimental process. The approach is exemplified on two engine control applications.
Dependable Systems and Networks, 2004 International Conference on;
