Publications (2)1.43 Total impact

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    ABSTRACT: Erratic bit phenomena have been reported in advanced flash memories, and have been attributed to trapping/detrapping effects that modify the threshold voltage. This paper describes for the first time the observance of erratic behavior in SRAM Vmin, defined as the minimum voltage at which the SRAM array is functional. Random telegraph signal (RTS) noise in the soft breakdown gate leakage is shown to be the cause. The erratic Vmin phenomenon can be eliminated for 90 nm SRAMs by process optimization. However, erratic Vmin behavior gets worse with smaller cell sizes and represents another constraint on the scaling of SRAM cells and on the minimum operating voltage of the SRAM array. A combination of process and circuit solutions will likely be needed to enable continued SRAM cell scaling
    Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
  • M. Agostinelli · S. Lau · S. Pae · P. Marzolf · H. Muthali · S. Jacobs
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    ABSTRACT: PMOS transistor degradation due to Negative Bias Temperature Instability (NBTI) has proven to be a significant concern to present CMOS technologies. This is of particular concern for analog applications where the ability to match device characteristics to a high precision is critical. Analog circuits use larger than minimum device dimensions to minimize the effects of process variation, leaving PMOS NBTI as a possible performance limiter. This paper examines the effect of PMOS NBTI induced mismatch on analog circuits in a 90nm technology.
    Reliability Physics Symposium Proceedings, 2004. 42nd Annual. 2004 IEEE International; 05/2004