-
Haizhou Yin,
M. Hamaguchi,
K.L. Saenger,
C.Y. Sung,
R. Hasumi,
K Ohuchi,
R Zhang,
J Cai,
J.A. Ott,
X Chen, [......],
N. Rovedo,
K. Fogel, G. Pfeiffer,
R. Kleinhenz,
D.K. Sadana,
M Takayanagi,
K. Ishimaru,
T.H. Ning,
D.-G. Park,
G. Shahidi
[show abstract]
[hide abstract]
ABSTRACT: End-of-range (EOR) defects generated during the crystal orientation conversion process in DSB technology can give rise to various types of junction leakage depending on their locations relative to device structures. A wide range of EOR defect depths are investigated. Shallow-implant-induced EOR defects (~100 nm) are found to minimize junction leakages due to EOR defects being outside of junction depletion regions. These implant conditions produce no adverse impact on source/drain channel leakage, suggesting that the crystal conversion process is optimized by shallow implants.
VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on; 05/2008
-
Haizhou Yin,
C.Y. Sung,
K.L. Saenger,
M. Hamaguchr,
R. Hasumi,
K. Ohuchr,
H. Ng,
R. Zhang,
K.J. Stein,
T.A. Wallner, [......], G. Pfeiffer,
R. Klemhenz,
R. Bendernagel,
D.K. Sadana,
M. Takayanagi,
K. Ishimaru,
S.W. Crowder,
D. Park,
M. Khare,
G. Shahidi
[show abstract]
[hide abstract]
ABSTRACT: When DSB bonding interface falls into highly doped S/D direct silicon bonded (DSB) technology is shown to be scalable regions, there are concerns of high S/D leakage (due to the possible for 32 nm node and beyond for two integration schemes: solid phase defects in the DSB interface) and high S/D resistance due to epitaxy (SPE)-before-shallow trench isolation (STI) and STI-before-SPE. For SPE-before-STI, 32 nm node ground rules can be met by thinning DSB thickness to ~70 nm, which ensures complete removal of boundary defects by STI. For STI-before-SPE, a scaling-independent solution is provided by the use of 45deg rotated (100) base wafers which allow trench-defect-free SPE at the STI edges.
VLSI Technology, 2007 IEEE Symposium on; 07/2007
-
Haizhou Yin,
C.Y. Sung,
H. Ng,
K.L. Saenger,
V. Chan,
S. Crowder,
R. Zhang,
J. Li,
J.A. Ott, G. Pfeiffer, [......],
K. Cheng,
A. Mesfin,
R. Kelly,
V. Ku,
Z.J. Luo,
N. Rovedo,
K. Fogel,
D.K. Sadana,
M. Khare,
G. Shahidi
[show abstract]
[hide abstract]
ABSTRACT: Two integration schemes for hybrid crystal orientation technology using direct silicon bonded (DSB) substrates and solid phase epitaxy (SPE) processes have been implemented. The shallow-trench-isolation (STI) before SPE approach suffers from trench-edge defects formed at STI edges, which causes high leakage current. The SPE-before-STI approach allows removal of edge defects of SPE by STI. SRAM in 65nm node and eDRAM in 90nm node have been demonstrated on DSB using the SPE-before-STI scheme
Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
-
Chun-Yung Sung,
Haizhou Yin,
H.Y. Ng,
K.L. Saenger,
V. Chan,
S.W. Crowder,
Jinghong Li,
J.A. Ott,
R. Bendernagel,
J.J. Kempisty, [......],
R.T. Mo,
P.Y. Nguyen, G. Pfeiffer,
M. Raccioppo,
N. Rovedo,
D. Sadana,
J.P. de Souza,
Rong Zhang,
Zhibin Ren,
C.H. Wann
[show abstract]
[hide abstract]
ABSTRACT: High performance 65-nm technology (L<sub>poly</sub>=45nm, EOT=1.2nm) bulk CMOS has been demonstrated for the first time on mixed orientation substrates formed by using direct silicon bonded (DSB) wafers and a solid phase epitaxy (SPE) process. The pFET performance is improved by 35% due to hole mobility enhancement on (110) surfaces as compared to (100) surfaces. nFETs on SPE-converted (100) surfaces exhibit the same performance as those on (100) controls. Ring oscillators fabricated using DSB with SPE show improvements of more than 20% compared with control CMOS on (100) surfaces
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
-
Haizhou Yin,
Z. Ren,
H. Chen,
J. Holt,
X. Liu,
J.W. Sleight,
K. Rim,
V. Chan,
D.M. Fried,
Y.H. Kim,
J.O. Chu,
B.J. Greene,
S.W. Bedell, G. Pfeiffer,
R. Bendernagel,
D.K. Sadana,
T. Kanarsky,
C.Y. Sung,
M. Ieong,
G. Shahidi
[show abstract]
[hide abstract]
ABSTRACT: Various local stress techniques have been integrated on strained-Si directly on insulator (SSDOI) substrates, including dual stress liner (DSL), stress memory technique (SMT), and embedded SiGe (eSiGe) in source/drain. SMT shows mild drive current enhancement on nFETs. PFETs with eSiGe exhibit significant enhancement, suggesting eSiGe compatibility with SSDOI is excellent. A ring oscillator delay of 3ps is achieved at leakage current of 1 muA/mum and V<sub>DD</sub>=1.1V
VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on;
