C.-H. Jan,
P. Bai,
J. Choi,
G. Curello,
S. Jacobs,
J. Jeong,
K. Johnson,
D. Jones,
S. Klopcic,
J. Lin, [......],
G. Sacks,
B. Turkot,
Y. Wang,
L. Wei,
J. Yip,
I. Young,
K. Zhang,
Y. Zhang,
M. Bohr,
B. Holt
[show abstract]
[hide abstract]
ABSTRACT: A leading edge 65nm logic process technology employing uni-axial strained silicon transistors has been optimized for ultra low power products. Record PMOS/NMOS drive currents of 0.38/0.66 mA/mum, respectively, have been achieved at 1.2V and off-state leakage of 100 pA/mum. Greater than 1000times reduction of SRAM cell standby leakage through implementation of sleep transistors and other leakage suppression schemes are also discussed
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006