S. Natarajan

Publications (2)0 Total impact

• Source

  Available from: lw23.com

  Conference Proceeding: A 65nm ultra low power logic platform technology using uni-axial strained silicon transistors

  C.-H. Jan, P. Bai, J. Choi, G. Curello, S. Jacobs, J. Jeong, K. Johnson, D. Jones, S. Klopcic, J. Lin, [......], G. Sacks, B. Turkot, Y. Wang, L. Wei, J. Yip, I. Young, K. Zhang, Y. Zhang, M. Bohr, B. Holt
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  ABSTRACT: A leading edge 65nm logic process technology employing uni-axial strained silicon transistors has been optimized for ultra low power products. Record PMOS/NMOS drive currents of 0.38/0.66 mA/mum, respectively, have been achieved at 1.2V and off-state leakage of 100 pA/mum. Greater than 1000times reduction of SRAM cell standby leakage through implementation of sleep transistors and other leakage suppression schemes are also discussed
  Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
• Source

  Available from: S. Sivakumar

  Conference Proceeding: An advanced low power, high performance, strained channel 65nm technology

  S. Tyagi, C. Auth, P. Bai, G. Curello, H. Deshpande, S. Gannavaram, O. Golonzka, R. Heussner, R. James, C. Kenyon, [......], N. Lindert, M. Liu, R. Nagisetty, S. Natarajan, C. Parker, J. Sebastian, B. Sell, S. Sivakumar, A. St Amour, K. Tone
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  ABSTRACT: An advanced low power, strained channel, dual poly CMOS 65nm technology with enhanced transistor performance is presented. At 1V and off current of 100nA/mum, transistors have record currents of 1.21mA/mum and 0.71mA/mum for NMOS and PMOS respectively. This industry leading 65nm technology is currently in high volume manufacturing
  Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006