P.S. Lim

Taiwan Semiconductor Manufacturing Company Limited, Hsin-chu-hsien, Taiwan, Taiwan

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Publications (6)6.58 Total impact

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    ABSTRACT: In this paper, a novel surface treatment technique using Silicon Surface Pre-Treatment (SSPT) technique to boost high performance CMOS circuit is reported. This approach provides a smooth silicon surface and extends the effective channel width to enhance device performance on both N and PMOSFET In this work, a smooth and rounded active area (AA) surface was successfully fabricated. Using this technique, we demonstrated a significant device boost of 15% and 7% on small dimension N and PMOSFET, respectively. These achievements were demonstrated without negative impact on GOI and NBTI.
    VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on; 05/2008
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    ABSTRACT: The dependence of the gate tunneling current (Jg) on nitrogen profile (N profile) within an ultrathin silicon oxynitride film is reported. It was found that gate tunneling current is dependent on N profile, even with equal oxide thickness and nitrogen dosage. Gate tunneling current increased with steeper N profile, and it had higher sensitivity for p-type metal-oxide-semiconductor field-effect transistor (MOSFET) than n-type MOSFET. A direct tunneling model based on Wentzel-Kramers-Brillouin approximation has been proposed. The model described the influence of N profiles on gate tunneling current through local change of dielectric constant, band bending, and effective mass. Also, it reasonably explained the different Jg sensitivity in n-/p-MOSFETs, a phenomenon that has not been addressed in earlier publications.
    Applied Physics Letters 01/2008; 92(2):022112-022112-3. · 3.79 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, a novel surface treatment technique using Silicon Surface Pre-Treatment (SSPT) technique to boost high performance CMOS circuit is reported. This approach provides a smooth silicon surface and extends the effective channel width to enhance device performance on both N and PMOSFET In this work, a smooth and rounded active area (AA) surface was successfully fabricated. Using this technique, we demonstrated a significant device boost of 15% and 7% on small dimension N and PMOSFET, respectively. These achievements were demonstrated without negative impact on GOI and NBTI.
    01/2008;
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    ABSTRACT: This letter reports the engineering of effective work function (EWF) for tantalum carbide (TaC) metal gate on high-k gate dielectrics. The dependence of EWF on Si concentration in HfSiO as well as nitridation techniques is revealed. The EWF was extracted by both terraced oxide and terraced high-k techniques with the bulk and interface charges taken into account. The incorporation of Si in Hf-based dielectrics results in an increase of EWF, while the presence of N tends to decrease the EWF. Plasma nitridation is found to be more effective in lowering the EWF than a thermal nitridation. The phenomena can be explained by the modification of TaC/high-k interface dipole moment, which arises from the electronegativity difference for various interface bonds. Based on the above findings, we proposed a novel approach to reduce the EWF of TaC on HfSiON by using a thin HfO<sub>2 </sub> cap layer after optimizing the nitridation. The MOSFET results show that this technique is able to achieve a lower V<sub>t</sub> without degrading the device performance
    IEEE Electron Device Letters 04/2007; · 2.79 Impact Factor
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    ABSTRACT: A systematic study is performed on tantalum carbide (TaC) metal electrode on HfO<sub>2</sub> and HfSiON dielectrics using conventional CMOS process. TaC's effective work function (EWF) is estimated to be 4.28 eV on HfO<sub>2</sub> using Vfb~EOT methodology, where both interfacial oxide and high-K film thickness are varied and thus charge effect is corrected successfully. Investigation of the EWF dependence on underlying dielectrics reveals that TaC EWF on HfSiON is about 0.17eV higher than that on HfO<sub>2</sub>. This phenomenon cannot be explained by the usual metal induced gap states (MIGS) theory. In addition, mobility higher than 90% of poly/SiO<sub>2</sub> reference and EOT scaling down to 12.5A has been achieved. Reduction of HfO<sub>2</sub> thickness is identified as an effective approach to suppress charge trapping in the gate stack. With reduced thickness, threshold voltage stability and electron mobility are significantly improved. All these results prove that TaC/high-K stack is a promising candidate in nMOSFET application
    Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
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    ABSTRACT: A study on the impacts of varying base oxide thickness, Si composition and nitridation on HfSiO to the overall high-k gate stack performance was carried out in detail. Increasing base oxide thickness from 8A to 12A was found to reduce susceptibility of charge trapping within HfSiO layer and improve drive current. Also, increasing Si composition in HfSiO layer from 50% to 75% produced a higher drive current. However, this improvement was achieved at the expense of a higher gate leakage current. The HfSiO, when subjected to N<sub>2</sub> plasma, forms HfSiON that exhibits excellent high-k dielectric properties with low EOT, low leakage current: and high driving current. With complete understanding on the contribution from each layer, a good high-k gate stack, based on HfSiON was fabricated. Leakage current was successfully reduced to three orders lower than the conventional SiO<sub>2</sub>.
    Integrated Circuit Design and Technology, 2004. ICICDT '04. International Conference on; 02/2004