[Show abstract][Hide abstract] ABSTRACT: Test chips built in a 32 nm bulk CMOS technology consisting of hardened and non-hardened sequential elements have been exposed to neutrons, protons, alpha-particles and heavy ions. The radiation robustness of two types of circuit-level soft error mitigation techniques has been tested: 1) SEUT (Single Event Upset Tolerant), an interlocked, redundant state technique, and 2) a novel hardening technique referred to as RCC (Reinforcing Charge Collection). This work summarizes the measured soft error rate benefits and design tradeoffs involved in the implemented hardening techniques.
[Show abstract][Hide abstract] ABSTRACT: In this paper, mitigation techniques to reduce the increased SEU cross section associated with charge sharing in a 90-nm dual-interlocked-cell latch are proposed. The increased error cross section is caused by heavy-ion angular strikes depending on the direction of the ion strike, thereby exacerbating charge sharing among multiple circuit nodes. The use of nodal spacing as a mitigation technique shows an order of magnitude decrease on upset cross section as compared to a conventional layout, and the use of guard-rings show no noticeable effect on upset cross section.
IEEE Transactions on Device and Materials Reliability 07/2009; 9(2-9):311 - 317. DOI:10.1109/TDMR.2009.2019963 · 1.89 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: The minimum laser energy required to cause sustained harmonic oscillations in a 201-stage ring oscillator varies little with increasing power supply voltage when operating in the subthreshold region. These small changes in threshold laser energy in the subthreshold region suggest that the cross-section curves as a function of power supply voltage remain relatively constant. Simulations show that the minimum pulsewidth required to generate higher-order oscillations decreases as operating voltage increases. Single-event transients are wider when circuits are operating in the subthreshold region than when operating at the nominal power supply voltages. Narrower single-event transients result for strikes on PMOS transistors as compared to those for strikes on NMOS devices in the subthreshold region; the opposite is observed when circuits are operating at the nominal power supply voltages.
[Show abstract][Hide abstract] ABSTRACT: Most pulse width characterization circuits measure single-event transients (SETs) using a target circuit consisting of long inverter chains or temporal latches exposed to heavy-ions over extended periods of time. For these approaches, circuit-level effects eliminate shorter pulses due to prolonged heavy-ion exposure providing the worst case estimate of measurable transients. Simulation results in the IBM 180 nm and 90 nm technologies corroborate this effect and discuss the resulting factors affecting single event (SE) error cross-sections. Experimental evaluation of such a SET pulse width characterization circuit under heavy-ion exposure showed reduced number of events measured due to total dose effects as expected. Additional experimental and simulation results show that the length of the propagation chains in the target circuit (for capturing SETs), the exposed flux and time (total dose) affect the resulting number of SEs measured.
[Show abstract][Hide abstract] ABSTRACT: SEUs due to combinational logic in 90 nm CMOS is analyzed at various speeds using a new design approach called the combinational circuit for radiation effects self-test (C-CREST). C-CREST allows the cross-section of combinational logic to be increased while minimizing propagation delay. The design was fabricated in IBM's 9SF CMOS process and underwent broadbeam testing that distinguished combinational logic errors from latch errors. Results confirm that the design is effective in testing combinational logic for SE vulnerabilities with minimum speed penalty.
[Show abstract][Hide abstract] ABSTRACT: A built-in self-test technique for testing digital logic circuits for single-events has been developed. The BIST technique can be used for single-event testing in any conventional laboratory to evaluate the circuit level response to SEs. Experimental and simulation results for multiple technology nodes show the feasibility of this approach to test circuits, with the added advantages of reduced testing time and cost.
[Show abstract][Hide abstract] ABSTRACT: Mitigation techniques to reduce the increased SEU cross-section associated with charge sharing in a 90 nm DICE latch are proposed. The increased error cross-section is caused by heavy ion angular strikes depending on the directionality of the ion vector, thereby exacerbating charge sharing among multiple circuit nodes. The use of nodal separation as a mitigation technique shows an order of magnitude decrease on upset cross-section compared to a conventional layout and the use of guard-rings show no noticeable effect on upset cross-section.
[Show abstract][Hide abstract] ABSTRACT: Random dopant fluctuation (RDF) induced threshold voltage variations affect two critical parameters used as a measure of single event (SE) hardness (i) single event transient (SET) pulse widths and (ii) critical charge . This causes an increase in the spread of SET pulse widths in sequential logic circuits and in the required for single event upsets (SEUs) in static random access memory cells (SRAMs). Monte Carlo simulations show this can affect the hardness characterization in a commercial 90 nm process and a generic 65 nm technology. This necessitates statistical design approaches for validating conventional hardening schemes, to assure a required level of radiation tolerance in these deep sub-micron technologies.
[Show abstract][Hide abstract] ABSTRACT: The presence of Single Event (SE) interconnect crosstalk has been demonstrated experimentally in the IBM 90 nm CMOS9SF process. Single and Two Photon pulsed laser experiments were performed to demonstrate this phenomenon. 3D mixed-mode simulations and modeling show SE interconnect crosstalk to depend on the interconnect length and on the amount of deposited charge. Simulations have been performed at the dual operating voltages used in this technology. Experimental and accompanying simulation results show this effect to increase SE susceptibility by increasing the vulnerable area and require evaluation to assure expected hardness levels.
Radiation and Its Effects on Components and Systems, 2007. RADECS 2007. 9th European Conference on; 10/2007
[Show abstract][Hide abstract] ABSTRACT: In the soft error domain, the critical charge Q<sub>crit</sub>is used as a measure to determine if a memory cell can be upset, and on that single value most hardening techniques are based. Inaccurate estimates of the critical charge can lead to failure of hardening schemes causing space-based and terrestrial electronics to malfunction leading to prohibitive losses in cost and yield. With the design for manufacturability (DFM) becoming an issue in advanced technologies as process variation worsens, the statistical modeling of variations in threshold voltage leads to a wider range of critical charge. This paper quantifies the spread in critical charge required for an upset due to statistical variations in threshold voltage in the IBM 130 nm and 90 nm technologies. Design guidelines to account for the spread in Q<sub>crit</sub> for an SEU in SRAM cells can be developed from simulations performed to estimate effective SER rates for memory cells.
[Show abstract][Hide abstract] ABSTRACT: Four different latch designs are evaluated using heavy ion exposure and simulations. The latches were designed using the Transition AND Gate (TAG) in TSMC 0.35 mum technology. TAG based designs were less vulnerable at lower LETs as compared to unhardened designs. However, 1- and 3-TAG design vulnerability increased at a higher rate with increasing LET than the unhardened design. 4-TAG design did not show any upsets until 170 MeV/mg/cm <sup>2</sup>. Simulation results are used to explain the behavior of each of the designs
[Show abstract][Hide abstract] ABSTRACT: In deep sub-micron technologies, scaling and closely packed interconnects magnify crosstalk effects causing a Single Event Transient (SET) pulse to affect multiple logic paths instead of the single hit path. Such events increase the vulnerable area and the SET susceptibility of complementary metal-oxide-semiconductor (CMOS) circuits. This paper analyses factors affecting the crosstalk pulse due to an Single Event Upset (SEU) in digital logic circuits for advanced technologies. Simulation results obtained substantiate that the effects of Single Event (SE) crosstalk increase as devices scale down, as the amount of charge deposited to cause an upset increases, and as the interconnect length increases
[Show abstract][Hide abstract] ABSTRACT: Hardening-by-design techniques to mitigate the effect of single-event transients (SET) using guard-gates are developed. Design approaches for addressing combinational logic hits and storage cell hits are presented. Simulation results show that the designs using guard-gates are less susceptible to single-event hits. Area, power, and speed penalty for guard-gate designs for combinational logic are found to be minimal. For latches, the area penalty is higher but speed penalty is minimal.