H. Gossner

Infineon Technologies, München, Bavaria, Germany

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Publications (102)78.2 Total impact

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    ABSTRACT: A comprehensive model of a clock line including large and small signal pin parameters, as well as channel parameters is presented. The small signal model allows analysis of in-band interference which can lead to soft failures, while large signal models allow for the simulation of current sharing between driver/receiver pin pairs.
    Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2014 36th; 07/2014
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    ABSTRACT: A comprehensive study of electrostatic discharge (ESD) characterization of atomically thin graphene is reported. In a material comprising only a few atomic layers, the thermally destructive second breakdown transmission line pulsing (TLP) current (It2) reaches a remarkable 4 ${rm mA}/mu{rm m}$ for 100-ns TLP and ${sim}{rm 8}~{rm mA}/mu{rm m}$ for 10-ns TLP or an equivalent current density of ${sim}3times 10^{8}$ and $4.6times 10^{8}~{rm A}/{rm cm}^{2}$ , respectively. For ${sim}{rm 5}hbox{-}{rm nm}$ thick $({sim}{rm 15}~{rm layers})$ graphene film, It2 reaches 7.4 ${rm mA}/mu{rm m}$ for 100-ns pulse. The fact that failure occurs within the graphene and not at the contacts indicates that intrinsic breakdown properties of this new material can be appropriately characterized using short-pulse stressing. Moreover, unique gate biasing effects are observed that can be exploited for novel applications including robust ESD protection designs for advanced semiconductor products. This demonstration of graphene's outstanding robustness against high-current/ESD pulses also establishes its unique potential as transparent electrodes in a variety of applications.
    IEEE Transactions on Electron Devices 06/2014; 61(6):1920-1928. DOI:10.1109/TED.2014.2315235 · 2.36 Impact Factor
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    ABSTRACT: Electrostatic discharge (ESD) investigations on the multiwalled carbon nanotubes (MWCNTs) are performed for the first time. A novel ESD failure mechanism of subsequent shell burning has been discovered. By using nanosecond pulse measurements, a new insight into metal-to-carbon nanotube (CNT) contact behavior could be achieved. Clear signature of two very different conduction mechanisms and related failure types at high current injection has been found. By determining the time to failure, an Arrhenius-like relation was extracted, which was explained by the oxidation of CNT shells. Finally, an extraordinary ESD failure current density of MWCNT of $hbox{1.2} times hbox{10}^{9} hbox{A/cm}^{2}$ could be shown.
    IEEE Transactions on Device and Materials Reliability 03/2014; 14(1):555-563. DOI:10.1109/TDMR.2013.2288362 · 1.54 Impact Factor
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    ABSTRACT: This paper presents a device-circuit co-design approach to achieve a low swing, high speed 1.2-5 V level shifter (LS) using drain extended MOS (DeMOS) transistors for system on chip applications in advance CMOS technologies. Limiting factors of the high-voltage devices during transients are identified and accordingly it is shown that the maximum operating frequency of traditional LS can be increased by at least a factor of two. It is demonstrated that optimization of key device parameters of the DeMOS transistor enhances the maximum clock frequency to more than 1 GHz while preserving the device breakdown voltage and duty cycle of the level shifted signal.
    IEEE Transactions on Electron Devices 11/2013; 60(11):3827-3834. DOI:10.1109/TED.2013.2283421 · 2.36 Impact Factor
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    ABSTRACT: Advanced mobile applications demand low power and high performance systems. In this paper, a technology computer aided design (TCAD)-based feasibility investigation of a recently proposed area tunneling field effect transistor (FET) structure is carried out from the point of high volume and ultralow power mobile applications. We demonstrate that for realization of future ultralow power and high performance systems, unique properties of area tunneling class of tunnel FET structures need to be employed. These devices are realized by engineering the tunneling region profile and tunneling cross-sectional area. The optimized devices are found to leverage up to ~ 7× energy reduction when compared with the 20-nm node MOS device options while meeting the high performance targets. Device design insights for such an area tunneling class of tunnel FET structures are discussed in this paper for the first time. It is shown that by lowering the supply voltage below 0.5 V, up to 10× reduction of the energy delay product is feasible by using area tunneling devices.
    IEEE Transactions on Electron Devices 08/2013; 60(8):2626-2633. DOI:10.1109/TED.2013.2270566 · 2.36 Impact Factor
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    ABSTRACT: The phenomenon of impact-ionization is proposed to be leveraged for a novel biosensor design scheme for highly efficient electrical detection of biological species. Apart from self-consistent numerical simulations, an analytical formalism is also presented to provide physical insight into the working mechanism and performance of the proposed sensor. It is shown that using the impact-ionization field-effect-transistor (IFET) based biosensor, it is possible to obtain an increase in sensitivity of around 4 orders of magnitude at low biomolecule concentration and around 6 orders of magnitude at high biomolecule concentration compared to that in conventional FET (CFET) biosensors. Moreover, IFET biosensors can lead to significant reduction (around 2 orders of magnitude) in response time compared to CFET biosensors.
    Applied Physics Letters 05/2013; 102(20). DOI:10.1063/1.4804577 · 3.52 Impact Factor
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    ABSTRACT: A gas-sensor based on tunnel-field-effect-transistor (TFET) is proposed that leverages the unique current injection mechanism in the form of quantum-mechanical band-to-band tunneling to achieve substantially improved performance compared to conventional metal-oxide-semiconductor field-effect-transistors (MOSFETs) for detection of gas species under ambient conditions. While nonlocal phonon-assisted tunneling model is used for detailed device simulations, in order to provide better physical insights, analytical formula for sensitivity is derived for both metal as well as organic conducting polymer based sensing elements. Analytical derivations are also presented for capturing the effects of temperature on sensor performance. Combining the developed analytical and numerical models, intricate properties of the sensor such as gate bias dependence of sensitivity, relationship between the required work-function modulation and subthreshold swing, counter-intuitive increase in threshold voltage for MOSFETs and reduction in tunneling probability for TFETs with temperature are explained. It is shown that TFET gas-sensors can not only lead to more than 10 000× increase in sensitivity but also provide design flexibility and immunity against screening of work-function modulation through non-specific gases as well as ensure stable operation under temperature variations.
    Applied Physics Letters 01/2013; 102(2). DOI:10.1063/1.4775358 · 3.52 Impact Factor
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    ABSTRACT: In this paper an advanced system-level TLP probing technique is presented to evaluate the ESD and EMI performance of a powered system applicable to high speed interfaces. It allows to detect hardware and software fail thresholds to assess the performance of an ESD/EMI protection solution. The method is demonstrated on a Intel mobile phone reference platform.
    Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2013 35th; 01/2013
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    ABSTRACT: form only given. Have you ever wondered how other companies organize their ESD design teams? Join us as we attempt to benchmark successful organization strategies as practiced by Workshop participant companies. We expect divergent opinions and a healthy debate on the advantages and disadvantages of the various approaches. Is your ESD design team embedded within an I/O design team, or independent? Are you in a central technology support organization, or in a product group? Does your company leverage outside ESD design contractors? Does your ESD design team organization drive your ESD support model? For example are ESD design solutions full custom for each I/O library, or offered as generic solutions in a process technology? Do you have separate engineers for ESD IP design and SoC support? How many IP sets or SoCs is each engineer expected to support? This Workshop should give you valuable insight into industry ESD team organization strategies to discuss with your work peers and managers.
    Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2013 35th; 01/2013
  • H. Gossner
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    ABSTRACT: While CMOS downscaling approaches its limits, ESD protection design is facing significant challenges. Technology measures which facilitate further technology scaling enhance the sensitivity of the devices against ESD stress. At the same time demanding performance requirements more and more limit the options of circuit solutions for ESD protection. In consequence ESD qualification goals for ICs had to be reviewed and adjusted. However, the need of ESD robust systems cannot be compromised. To balance and match IC level protection and PCB protection measures the concept of system efficient ESD design (SEED) has recently been introduced.
    VLSI Circuits (VLSIC), 2013 Symposium on; 01/2013
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    ABSTRACT: A systematic method for evaluating soft fail robustness of a DUT subsystem is presented and demonstrated on a camera MIPI interface. Two different mobile phone platforms are studied under TLP injection while various methods for extracting failure thresholds and localization are applied. The root cause for the soft-failure threshold discrepancy is left for future work.
    Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2013 35th; 01/2013
  • M. Shrivastava, H. Gossner
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    ABSTRACT: This paper reviews electrostatic discharge (ESD) investigations on laterally diffused MOS (LDMOS) and drain-extended MOS (DeMOS) devices. The limits of the safe operating area of LDMOS/DeMOS devices and device physics under ESD stress are discussed under various biasing conditions and layout schemes. Specifically, the root cause of early filament formation is highlighted. Differences in filamentary nature among various LDMOS/DeMOS devices are shown. Based on the physical understanding, device optimization guidelines are given. Finally, an outlook on technology scaling is presented.
    IEEE Transactions on Device and Materials Reliability 12/2012; 12(4):615-625. DOI:10.1109/TDMR.2012.2220358 · 1.54 Impact Factor
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    ABSTRACT: A novel drain-extended FinFET device is proposed in this letter for high-voltage and high-speed applications. A 2 × better RON versus VBD tradeoff is shown from technology computer-aided design simulations for the proposed device, when compared with a conventional device option. Moreover, a device design and optimization guideline has been provided for the proposed device.
    IEEE Electron Device Letters 10/2012; 33(10):1432-1434. DOI:10.1109/LED.2012.2206791 · 3.02 Impact Factor
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    ABSTRACT: Based on 3-D TCAD simulations, a ten-times improvement in the ESD performance of drain-extended NMOS device is predicted by incorporating deep p-implant underneath the n+ drain region. The proposed modification does not degrade the intrinsic MOS characteristics, thus enabling a self-protection ESD concept. Moreover, a detailed physical insight toward the achieved improvement is given.
    IEEE Electron Device Letters 09/2012; 33(9):1294-1296. DOI:10.1109/LED.2012.2205553 · 3.02 Impact Factor
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    ABSTRACT: We report on the thermal failure of fin-shaped field-effect transistor (FinFET) devices under the normal operating condition. Pre- and postfailure characteristics are investigated. A detailed physical insight on the lattice heating and heat flux in a 3-D front end of the line and complex back end of line—of a logic circuit network—is given for bulk/silicon-on-insulator (SOI) FinFET and extremely thin SOI devices using 3-D TCAD. Moreover, the self-heating behavior of both the planar and nonplanar devices is compared. Even bulk FinFET shows critical self-heating. Layout, device, and technology design guidelines (based on complex 3-D TCAD) are given for a robust on-chip thermal management. Finally, an improved framework is proposed for an accurate electrothermal modeling of various FinFET device architectures by taking into account all major heat flux paths.
    IEEE Transactions on Electron Devices 05/2012; 59(5):1353-1363. DOI:10.1109/TED.2012.2188296 · 2.36 Impact Factor
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    ABSTRACT: The paper describes the essential requirements of the Electrostatic Discharge (ESD) EDA verification flow to be aligned within the IC design community. The proposed flow offers a systematic approach to check ESD robustness across all IC blocks during the product definition, chip architecture, main module and full IC design phases, and during the final IC verification. This flow is substantiated by case studies of key ESD checks at different IC design stages, demonstrating the necessity of replacing manual checks with EDA tool enabled verification.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012
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    ABSTRACT: A first-time study of ESD characterization of atomically-thin graphene is reported. In a material comprising only a few atomic layers, It2 reaches 4 mA/μm for 100 ns and ~8 mA/μm for 10 ns TLP or an equivalent current density of 2-3×108 A/cm2 and 4.6×108 A/cm2, respectively. The fact that failure occurs within the graphene and not at the contacts indicates that intrinsic properties of this new material can be appropriately characterized by using short-pulse stressing. Moreover, unique gate biasing effects are observed that can be exploited for novel applications including robust ESD protection designs for advanced semiconductor products.
    Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2012 34th; 01/2012
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    ABSTRACT: A hard-to-detect functional CDM ESD failure caused by an obscure charge trapping phenomenon on an advanced CMOS IC is described while no physical damage was evident. Advancing failure analysis method by localized thermal LASER annealing and applying analytical ESD test plan led to successful localization of the root cause.
    Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2012 34th; 01/2012
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    ABSTRACT: Improvement of ~5X in the I<sub>T2</sub> (3.3mA/μm) of a grounded gate N-DeMOS device compared to a standard design is achieved by simple layout variations with a minor impact on its footprint. Robustness of P-DeMOS devices is shown to be further increased by additional p implant in drain region. Electrical and thermal instabilities are studied by Transmission Line Pulsing (TLP), Transient Interferometric Mapping (TIM) method and 3D TCAD simulations.
    Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2011 33rd NO POD PERMISSION; 10/2011

Publication Stats

586 Citations
78.20 Total Impact Points

Institutions

  • 1999–2011
    • Infineon Technologies
      München, Bavaria, Germany
  • 2009–2010
    • Indian Institute of Technology Bombay
      • Department of Electrical Engineering
      Mumbai, State of Maharashtra, India
  • 1999–2010
    • Vienna University of Technology
      • Institute of Solid State Electronics
      Vienna, Vienna, Austria
  • 2008
    • KU Leuven
      • Department of Electrical Engineering (ESAT)
      Leuven, VLG, Belgium
  • 2007
    • Stanford University
      Palo Alto, California, United States
  • 2004
    • Technische Universität München
      • Lehrstuhl für Nukleartechnik
      München, Bavaria, Germany