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M. Fulde,
K.v. Arnim,
C. Pacha,
F. Bauer,
C. Russ,
D. Siprak,
W. Xiong, A. Marshall,
C.R. Cleavelin,
K. Schruefer,
D. Schmitt-Landsiedel,
G. Knoblinger
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ABSTRACT: In this paper recent advances in Multi-Gate MOS-FET (MuGFET) circuit design are reported. The feasibility of essential parts of low-power mobile SoC applications and large scale integration capability is shown. Excellent short channel control enables undoped metal gate MuGFETs to outperfom their planar counterparts in terms of delay-leakage trade-off. Superior voltage scaling efficiency and competitive performance is demonstrated for a product typical critical path. Design and layout optimization for improved SRAM cell stability is shown. Beneficial analog performance is exemplary demonstrated for an OpAmp. A potential degradation of ADC performance due to transient VT mismatch is shown, the use of redundancy is proposed as countermeasure. Key RF building blocks are presented, MuGFET specific design issues are outlined. A comparison of different ESD elements yields a potential ESD protection scheme combining planar and MuGFET devices.
Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on; 01/2008
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ABSTRACT: The availability of SOI from silicon foundries is making SOI a viable option for implantable electronics devices. The field has some specific needs that are different to many conventional electronics applications. Low power operation is essential but with intermittent high power requirements and the need for long term reliability. Conversely, circuit operating speed requirements are often extremely low; including monitoring at only a few KHz. Data storage (memory) requirements may also be relatively low. Furthermore, the operating temperature range of implanted devices is low compared to many non-implantable applications. These requirements together are assessed against the unique attributes of silicon on insulator (SOI) as a semiconductor material of choice for this environment, compared to that of conventional 'bulk' silicon.
Engineering in Medicine and Biology Workshop, 2007 IEEE Dallas; 12/2007
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G. Knoblinger,
M. Fulde,
D. Siprak,
U. Hodel,
K. Von Arnim,
T. Schulz,
C. Pacha,
U. Baumann, A. Marshall,
W. Xiong,
C.R. Cleavelin,
P. Patruno,
K. Schruefer
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ABSTRACT: In this paper we present for the first time essential building blocks for RF circuits in an advanced FinFET technology. Voltage controlled oscillators (VCOs) and a low noise amplifier (LNA) have been realized.
SOI Conference, 2007 IEEE International; 11/2007
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C. Pacha,
K. von Arnim,
F. Bauer,
T. Schulz,
W. Xiong,
K.T. San, A. Marshall,
T. Baumann,
C.R. Cleavelin,
K. Schruefer,
J. Berthold
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ABSTRACT: Energy dissipation, performance, and voltage scaling of multi-gate FET (MuGFET) based CMOS circuits are analyzed using product-representative test circuits composed of 10k devices. The circuits are fabricated in a low power MuGFET CMOS technology, achieve clock frequencies of 370-500MHz at VDD=1.2V, and operate down to the subthreshold region. Voltage scalability of MuGFET circuits is superior to sub-100 nm planar CMOS circuits due to excellent short-channel effect control.
37th European Solid State Device Research Conference, 2007. ESSDERC; 10/2007
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K. von Arnim,
E. Augendre,
A.C. Pacha,
T. Schulz,
K.T. San,
F. Bauer,
A. Nackaerts,
R. Rooyackers,
T. Vandeweyer,
B. Degroote,
N. Collaert,
A. Dixit,
R. Singanamalla,
W. Xiong, A. Marshall,
C.R. Cleavelin,
K. Schrufer,
M. Jurczak
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ABSTRACT: This paper presents an in-depth analysis of digital performance of a Multi-Gate FET technology. Ring oscillators with metal gates and undopedfins show an inverter delay of 13.9ps at 1V, the highest performance of a Multi-Gate FET technology reported at 1.9nA off-current/stage. NAND and NOR show significant improvement in delay vs. stack height compared to bulk CMOS. SRAM cells and product-typical critical paths with more than 10k transistors demonstrate the capability for large-scale integration.
VLSI Technology, 2007 IEEE Symposium on; 07/2007
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ABSTRACT: Electrostatic discharge (ESD) characteristics of fully depleted FinFET devices are presented and compared to planar structures manufactured in the same multiple-gate FET Technology. FinFET-type MOS devices in breakdown mode are found to show an unprecedented sensitivity to ESD stress, while planar devices and FinFET gated diodes perform reasonably and with - characteristics beneficial for ESD protection.
IEEE Transactions on Device and Materials Reliability 04/2007; · 1.54 Impact Factor
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C. Pacha,
K. von Arnim,
T. Schulz,
Weize Xiong,
M. Gostkowski,
G. Knoblinger, A. Marshall,
T. Nirschl,
J. Berthold,
C. Russ,
H. Gossner,
C. Duvvury,
P. Patruno,
R. Cleavelin,
K. Schruefer
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ABSTRACT: Multi-gate FETs are promising for sub-45nm CMOS technologies. To address the link between design and technology, basic digital and analog circuits are fabricated using FinFET and triple-gate FETs. Digital circuit performance, leakage currents, and power dissipation are characterized. The triple-gate FET achieves the lowest gate delay (27ps at 1.2V) and is >30% faster than FinFET with same oxide thickness of 2nm and gate lengths of 80nm. A FinFET-based Miller OpAmp achieves 45dB dc gain at 1.5V
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International; 03/2006
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A. Marshall,
M. Kulkarni,
M. Campise,
R. Cleavelin,
C. Duvvury,
H. Gossner,
M. Gostkowski,
G. Knoblinger,
C. Pacha,
C. Russ,
K. Schruefer,
T. Schulz,
K. VonArnim,
B. Wilks,
W. Xiong
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ABSTRACT: With trends toward smaller geometries and improved circuit performance continuing, an option being investigated is multigate FETs on SOI substrates. SOI lends itself to SOC systems due to its inherently lower noise and ease of integration of analog, digital, RF and power circuits. A critical analog circuit requirement is accurate current mirroring. Here characteristics of fully depleted FinFET current mirrors are presented. Silicon FinFET current mirrors and their bulk planar counterparts have similar performance and matching: a vital requirement for analog circuitry on this type of material.
Architecture, Circuits and Implementtation of SOCs, 2005. DCAS '05. Proceedings of the 2005 IEEE Dallas/CAS Workshop:; 11/2005
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G. Knoblinger,
F. Kuttner, A. Marshall,
C. Russ,
P. Haibach,
P. Patruno,
T. Schulz,
W. Xiong,
M. Gostkowski,
K. Schruefer,
C.R. Cleavelin
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ABSTRACT: Multi-gate MOSFET (MuGFET) are the most promising candidates for beyond 45nm technology CMOS nodes. For future SoC solutions in these technologies the ability to realize also analog building blocks is of utmost importance. Up to now only a few publications are available concerning the perspective of FinFETs for analog applications and no reports and measurement results can be found about the realization of analog circuits with these advanced devices. In this work the design and realization of basic analog circuits (low voltage bandgap, Miller op amp and current reference) with FinFET devices were demonstrated for the first time, including measurement results.
SOI Conference, 2005. Proceedings. 2005 IEEE International; 11/2005
