[Show abstract][Hide abstract] ABSTRACT: In this work we examine the influence of thermal oxidation on the electrical characteristics of ultra-thin strained silicon layers grown on relaxed Si0.78Ge0.22 substrates under moderate to high thermal budget conditions in N2O ambient at 800 °C. The results reveal the presence of a large density of interfacial traps which depends on the oxidation process. As long as the strained silicon layer remains between the growing oxide and the underlying Si0.78Ge0.22 layer, the density of interface traps increases with increasing oxidation time. When the oxidation process consumes the s-Si layer the interface state density undergoes a significant reduction of the order of 40%. This experimental evidence signifies that the strained silicon–Si0.78Ge0.22 interface is a major source of the measured interfacial defects. This situation can be detected only when the front SiO2-strained silicon interface and the rear strained silicon–Si0.78Ge0.22 interface are in close proximity, i.e. within a distance of 5 nm or less. Finally, the influence of the material quality deterioration—as a result of the thermal treatment—to the interfacial properties of the structure is discussed.
Thin Solid Films 06/2011; 519(16-16):5456-5463. DOI:10.1016/j.tsf.2011.02.085 · 1.76 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: In this work ultrathin strained silicon layers grown on relaxed Si <sub>0.9</sub> Ge <sub>0.1</sub> substrates were oxidized under high thermal budget conditions in N <sub>2</sub> O ambient at 800 ° C . The results indicate that the density of interface traps depends on the extent of the oxidation process. If the strained Si layer is totally consumed the density of interface traps reduces to almost half the value as compared to the case where a part of the strained Si layer still remains. The results indicate that the two existing interfaces of the strained Si layer, the SiO <sub>2</sub> /strained-Si and the strained- Si / Si <sub>0.9</sub> Ge <sub>0.1</sub> , contribute in parallel to the measured interface trap density. In addition, the buried strained- Si / Si <sub>0.9</sub> Ge <sub>0.1</sub> interface constitutes a major source of the observed high density of interface traps.
[Show abstract][Hide abstract] ABSTRACT: In this work the influence of thermal oxidation and subsequent thermal processing on the electrical characteristics of strained-Silicon (s-Si), MOS capacitors was studied. Strained-Si/Si1 − xGex/Si substrates of two different strain levels (10% and 22% Ge content) were oxidized within the temperature range of 800 °C to 900 °C for various time intervals. Capacitance-Voltage measurements reveal that the response of the MOS capacitors depends mainly upon two factors: a) the extend of the s-Si layer oxidation, i.e. the remaining s-Si thickness and b) the duration of the post-oxidation annealing in inert ambient. Both factors influence the interfacial properties of the structures. Additional oxidation experiments in N2O ambient indicate a significant influence of the process conditions on the quality of the oxidized structures.
Thin Solid Films 11/2008; 517(1). DOI:10.1016/j.tsf.2008.08.111 · 1.76 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: In the present work we perform a systematic study of oxidation of very low energy nitrogen-implanted strained-silicon in terms of oxide growth, structural characterization of the implanted strained-silicon substrate and electrical properties of the ultra thin oxides as a function of the substrate strain level. Low energy (3keV) nitrogen (N2+) implantation was performed in strained-Si/SiGe/Si substrates of various strain levels and oxidations were carried out for different times at 850°C. It has been found that nitrogen implantation efficiently blocks silicon oxidation, independently of the strain level of the substrate. TEM analysis revealed the full absence of extended defects in the strained-silicon substrate after the thermal treatments. The grown oxides exhibit very good electrical properties in terms of interface trap densities and leakage currents.
Materials Science and Engineering B 12/2006; 135(3):199-202. DOI:10.1016/j.mseb.2006.08.004 · 2.17 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: This paper demonstrates for the first time the scalability of source/drain current enhancement on low-doped thin film strained silicon on insulator (sSOI) substrate. Current improvement is maintained in narrow channel NFETs despite the relaxation from biaxial to uniaxial tensile strain after mesa patterning. Using strained contact etch-stop layers (sCESL), additional boost is achieved in short devices, resulting in 50% improvement in the drive current of 50 nm gate length devices with respect to conventional reference SOI process.
Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European; 10/2005
[Show abstract][Hide abstract] ABSTRACT: In this paper, the authors report Freescale Semiconductor and MEMC collaboration to provide SOI wafers with bottom gate structures, SiON/polysilicon and high-K/metal gates, under the single crystalline silicon channel layer