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ABSTRACT: 3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme with transmitter and receiver circuits implemented in 0.13mum CMOS technology and connected to 8x8mum<sup>2</sup> electrodes in the upper metal layer of different dies and with face-to-face assembly, makes available a throughput of more than 22Mbps/mum<sup>2</sup> with 80muW/Gbps energy consumption.
Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT 2008. IEEE International Conference on; 07/2008
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ABSTRACT: A wireless interconnection scheme based on capacitive coupling provides mono- and bi-directional transmission capabilities for 3-D system integration. Chips are implemented in 0.13 mum CMOS technology and assembled face-to-face at die-level. RX-TX circuits are specifically designed for low-power functionality and the implementation takes advantage of the two different voltage thresholds that are available for the standard transistors in the CMOS process we used. The communication circuits are coupled via electrodes with an area down to 8 times 8 mum<sup>2</sup> and this enables the vertical propagation of clock signals at 1.7 GHz, a propagation delay of 420 ps for general purpose signals and a throughput of more than 22 Mb/s/mum<sup>2</sup> with 0.08 pJ/b energy consumption.
IEEE Journal of Solid-State Circuits 02/2008; · 3.23 Impact Factor
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ABSTRACT: This paper presents a 3D interconnection scheme based on capacitive coupling. We propose synchronous communication circuits, based on a precharge and transmission approach, that provide an optimization of interconnection sensitivity. Measurements on a 0.13 ¿m CMOS implementation demonstrate working connections with an area occupation of 8 à 8 ¿m<sup>2</sup> . Experimental results are presented for both die-to-die and wafer-to-wafer assembly techniques. They show a maximum communication bandwidth of 1.23 Gb/s, leading to a throughput per area of 19 Mb/s/¿M<sup>2</sup> with an energy consumption of 0.14 mW/Gb/s. BER measurements demonstrate the reliability of these AC interconnections with no error on more than transmitted.
IEEE Journal of Solid-State Circuits 11/2007; · 3.23 Impact Factor
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ABSTRACT: A 3D interconnection scheme based on capacitive coupling for high speed chip to chip communication has been implemented in a 0.13 mum CMOS process. This paper provides detailed design example for both synchronous and asynchronous transmitter and receiver circuits. The first approach shows with electrodes 15 times 15 mum<sup>2</sup> a wide range of operating frequency up to 900 MHz with an energy consumption of 41fJ/bit. In the asynchronous scheme we demonstrate with electrodes 8 times 8 mum<sup>2</sup> a vertical propagation of clock at 1.7 GHz and a propagation delay of 420 ps for general purpose signal with energy consumption of 80 f J/bit. Functionality and performance have been demonstrated by using both die-level and wafer-level assembly flows and BER measurements show the reliability of these AC interconnections with no error on more than 10<sup>13</sup> bits transmitted.
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE; 10/2007
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ABSTRACT: This paper presents a synchronous 3D interconnection based on capacitive coupling. The designed link presents a power consumption of 0.128mW/pin@975Mbps/pin, overcoming standard I/O pads performance of two orders of magnitude. High bit-rate, reduced power consumption and electrode area down to 8×8μm<sup>2</sup> enable the implementation of highly parallel pipelined interfaces for inter-chip communication, with an aggregate consumption of about 0.14mW/Gbps.
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005; 10/2005
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ABSTRACT: This paper presents an electronic system based on integrated CMOS capacitive sensors that enables to determine the alignment between two chips assembled in a three-dimensional (3D) stacking configuration. Two different interface circuits are described for the on-chip measurement of alignment along vertical Z-axis and lateral X/Y-axis. A test chip has been fabricated in 0.13μm, 6 metal standard CMOS process to test the multi-axis alignment system based on 3D sensors. A capacitive charge variation of 1 fF over 15fF corresponding to a resolution accuracy of 0.5μm over a range of 50μm has been measured. Sensors are 120μm × 30μm and power consumption is 200μW.
Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European; 10/2005
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ABSTRACT: Chip-to-chip interconnection, based on wireless communication by capacitive coupling was investigated. This innovative approach will considerably reduce the pitch of the pin and strongly help in the implementation of a dense network of interconnects, while improving inter-chip bandwidth and power dissipation. The 3D integration technology based on aligned wafer-to-wafer direct bonding technique was implemented for IC capacitive interconnection realization. The capacitive structures are created by facing two wafers with symmetrical IC chips bearing at last level a two-dimensional array of metal arms covered by a dielectric layer. Communication take place by capacitive coupling using capacitors created at location in the aligned micro-array. The capacitance dielectric thickness was monitored during the wafer bonding. Specific wafer process flow and especially precise circuit alignment were applied; in order to create between the bonded chips the capacitive interconnect arrays. After bonding, one wafer was thinned down, and I/O via were opened though the piled up remaining silicon and the two bonded stacks of CMOS structures. That elaborated structure was then ready for wire bonding. Electrical characterization tests are performed and the first functional testing gives very good performances in high-speed communication between the stacked chips.
Microelectronic Engineering.
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ABSTRACT: Capacitive interconnections are very promising structures for high-speed and low-power signaling in 3D packages. Since the performance of AC links, in terms of Band-Width and Bit-Error-Rate (BER), depends on assembly and synchronization accuracy we performed a statistical analysis of assembly procedures and communication circuits. In this paper we present a yield prediction methodology for 3D capacitive links: starting from the analysis of communication circuits and BER measurements, we analyze stacking variability in order to predict reliability and performance. The proposed parametric yield analysis is demonstrated on a test-case, with constrained inter-electrode coupling and operating frequency.
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ABSTRACT: For heterogeneous chip technologies (Power/Signal, Electronics/MEMS, CMOS/III-V’s, ...) the three dimensional integration of hybrid assembled chips is a viable approach to overcome the issues encountered here. Especially when the interconnects become very dense (high I/O’s) or signal voltages from chip to chip are vastly different, a non-ohmic contact via capacitive coupling can be a solution to overcome this issue. Submicron accuracies in the z-direction and low-micron accuracies in x/y are required to fulfill the needs of such a capacitive contact for 8x8µm2 sized pad arrays. The authors have successfully developed a chip, the interconnect scheme and the assembly process that allows the capacitive coupling of high I/O chips for electronic, MEMS and heterogeneous hybrid devices. The 3D Chip Stack was afterwards assembled on a test PCB with through via wirebonding. Envisioned concept shows the use of backside contacts e.g. PWR/GND/CLK for the top chip to be realized by integrated through via chip manufacturing as used in MEMS/MOEMS technology
Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS - DTIP’06, 26-28 April 2006, Stresa, Lago Maggiore, Italy, 5 p.
