Tero Tikka

Aalto University, Helsinki, Uusimaa, Finland

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Publications (13)7.42 Total impact

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    ABSTRACT: This paper presents a fully integrated 40-GHz transceiver designed for 2 Gbit/s short-range chip-to-chip communication link. The proposed architecture includes both the transmitter and the receiver and is optimized for on-off-keying modulation scheme. The transceiver design includes two variants, which can drive either a planar on-chip antenna or wire-bonded off-chip antenna. The performance comparison of these is given in the paper. A compact and energy-efficient technique has been adopted by directly modulating the oscillator in the transmitter. The receiver uses a self-mixing topology followed by transimpedance amplifier and a limiter chain. The detailed circuit descriptions as well as design trade-offs with simulation results in 65 nm CMOS are given. In addition, an example design modification to extend the modulation to 4-level amplitude shift keying is presented.
    Analog Integrated Circuits and Signal Processing 04/2015; 83(1). DOI:10.1007/s10470-015-0501-7 · 0.40 Impact Factor
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    ABSTRACT: This paper presents a clock generator for a MIPI M-PHY serial link transmitter, which includes an ADPLL, a digitally controlled oscillator (DCO), a programmable multiplier, and the actual serial driver. The paper focuses on the design of a DCO and how to enhance the frequency resolution to diminish the quantization noise introduced by the frequency discretization. As a result, a 17-kHz DCO frequency tuning resolution is demonstrated. Furthermore, implementation details of a low-power programmable 1-to-2-or-4 frequency multiplier are elaborated. The design has been implemented in a 40-nm CMOS process. The measurement results verify that the circuit provides the MIPI clock data rates from 1.248 GHz to 5.83 GHz. The DCO and multiplier unit dissipates a maximum of 3.9 mW from a 1.1 V supply and covers a small die area of 0.012 mm2.
    2014 IEEE International Symposium on Circuits and Systems (ISCAS); 06/2014
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    ABSTRACT: A scalable low-voltage signaling (SLVS) serial link transmitter for MIPI M-PHY is presented in this paper. It delivers 200-400 mV pp signals at date rates of 1.25-5.8 Gbps. The integrated circuit entity consists of the actual SLVS driver, an ADPLL-based clock synthesizer with a frequency multiplier, and an internal test signal generator with pseudo-random binary sequences. The circuit has been fabricated in a 40-nm CMOS process. The overall active die area is 0.2 mm(2), while the actual driver occupies only 190 mu m(2). In this work it was confirmed that a low-power SLVS driver meets the stringent common-mode noise generation limits set for serial interfaces used in mobile devices. Noise power density remains below -138 dBm/Hz at all data rates. Total power consumption of the transmitter is kept low by utilizing dynamic CMOS pre-drivers and a low drop-out voltage regulator. It achieves power efficiency of 0.44-1.4 mW/Gbps with external clock and 2.6-4.7 mW/Gbps with clock synthesizer.
    Analog Integrated Circuits and Signal Processing 01/2014; 82(1):159-169. DOI:10.1007/s10470-014-0433-7 · 0.40 Impact Factor
  • Tero Tikka, Jussi Ryynänen
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    ABSTRACT: This paper presents a 30-39 GHz 2Gbit/s OOK modulator targeted for chip-to-chip communications. The design is based on a 10 to 13 GHz ring oscillator with three times frequency multiplier, and an embedded 2 Gbit/s data feed. The detailed circuit description as well as analysis to estimate the effect of component mismatches to both ring oscillator and frequency multiplier performance is given in this paper.
    International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France; 01/2010
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    ABSTRACT: In this work, a system model for RF wireless interconnect has been proposed based on digital on-off keying (OOK) modulated RF transceiver with 2 Gb/s transmission rate and 40 GHz carrier frequency. To evaluate performance of wireless interconnect, the impact of critical non-idealities caused by circuit blocks has been analyzed and simulated in Matlab<sup>®</sup> Simulink<sup>®</sup> environment. A set of rough circuit specifications and BER performances of such system are obtained, through which key points during actual circuit design has come into view. The result of this work has verified the potential feasibility and reliability, and pointed out possible circuit design stresses for wireless interconnect system.
    NORCHIP, 2009; 12/2009
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    ABSTRACT: We present design aspects and techniques for millimeter-wave circuits implemented in 65-nm CMOS. Different transmission line topologies are discussed and measurement results for a conventional coplanar waveguide and slow-wave coplanar waveguide implemented in 65-nm CMOS are shown. The attenuation of the on-chip transmission lines can be reduced by using slow-wave coplanar waveguides. A 1-stage cascode amplifier in 65-nm CMOS employing inductors as matching elements is presented. On-chip interconnections of the amplifier are implemented and modeled using coplanar waveguides. The ground plane of the coplanar waveguide provides a good ground reference for the entire circuit.
    Microwave Integrated Circuit Conference, 2008. EuMIC 2008. European; 11/2008
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    ABSTRACT: In this paper, a design of an integrated receiver for base-station applications is presented. The receiver is targeted to cover all WCDMA bands and the WiMAX band below 4 GHz. The receiver includes RF front-end, 90-degree phase shifters and programmable baseband filters. The measured voltage gain and NF of the receiver at 2 GHz is 32 dB and 2.6 dB, respectively. The receiver is implemented using a 0.25-mum SiGe BiCMOS process and the power consumption is 432.5 mW from a 2.5 V supply.
    Radio and Wireless Symposium, 2008 IEEE; 02/2008
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    ABSTRACT: This paper focuses on the design and measurements of low-noise amplifiers (LNA) targeted for WCDMA base-station applications. In addition, various gain control techniques and the accuracy in noise measurements have been analyzed. Two different LNA designs are presented. Both LNAs can be operated in two gain modes, which are optimized for different base-station configurations. Both designs are implemented using the same 0.25-μm SiGe BiCMOS process, and both designs achieve the NF of 1 dB and IIP3 of −5 dBm in high gain mode.
    Analog Integrated Circuits and Signal Processing 01/2008; 54(2):105-111. DOI:10.1007/s10470-007-9069-1 · 0.40 Impact Factor
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    ABSTRACT: This paper describes design issues related to high linearity SiGe BiCMOS active mixers, which are primarily targeted for WCDMA base-station applications. The effect of different mixer components to overall mixer dynamic range is described, and the measurement results from four different implementations are given to support this discussion. The different mixers are implemented using the same process as part of a complete receiver and thus the interface to baseband filter has been taken into account in the performance analysis. Since one of the goals in the mixer design has been to maximize the mixer bandwidth, the frequency limitations of different alternatives are discussed throughout the paper.
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    ABSTRACT: The multicarrier receiver IC described in this paper receives four adjacent WCDMA channels simultaneously in order to reduce the component count of a base-station. The receiver uses low-IF architecture and it is fabricated with a 0.25-mum SiGe BiCMOS process to meet the high-performance requirements set by the base-station application. The receiver includes a dual-input low-noise amplifier (LNA), quadrature mixers, a local-oscillator (LO) divider, IIP2 calibration circuits, 10-MHz low-pass filters, and ADC buffers. The receiver noise figures, measured over the downconverted WCDMA channels centered at 2.5-MHz and 7.5-MHz intermediate frequencies, are 3.0 dB and 2.6 dB, respectively. The receiver achieves 47-dB voltage gain and -12-dBm out-of-band IIP3 and consumes 535mW from a 2.5-V supply
    IEEE Journal of Solid-State Circuits 08/2006; DOI:10.1109/JSSC.2006.873924 · 3.11 Impact Factor
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    ABSTRACT: A base-station receiver, which is capable of receiving from one to four adjacent WCDMA channels, is described in this paper. The receiver is designed to drive high-resolution Nyquist-rate A/D converters and it can be used as a direct-conversion receiver (DCR) or as a low-IF receiver in WCDMA bands I-III. The low-IF NF is 2.7/3.0 dB for the channels centered at 7.5 MHz and 2.5 MHz, respectively. The measured IIP3 of the receiver varies from -10 dBm to -8 dBm depending on the number of the received channels. The power consumption is 542.5 mW from a 2.5-V supply
    Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 IEEE; 07/2006
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    ABSTRACT: The design of a high linearity current-mode mixer, which is targeted for base-station (BS) direct-conversion receiver, is described in this paper. Several different configurations based on the Gilbert cell mixer are compared to achieve a high input referred third-order interception point (IIP3) performance with a low noise figure (NF). According to the simulations the designed mixer achieves +15-dBm IIP3 and 10-dB NF. The mixer draws 7 mA from a 2.5-V supply and has been fabricated with a 0.25-mum SiGe BiCMOS process
    Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on; 06/2006
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    ABSTRACT: A multicarrier receiver, which is capable of receiving four parallel WCDMA channels, is described in this paper. The receiver is targeted for base-station applications and designed to drive high-resolution Nyquist-rate A/D converters. The multicarrier receiver achieves 2.6-dB / 3.0-dB NF at the WCDMA channels centered at 2.5 MHz and 7.5 MHz, respectively. The IIP3 for all four WCDMA channels is -12-dBm, and the receiver consumes 535 mW from a 2.5-V supply.
    Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European; 10/2005