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ABSTRACT: Calibrated 3-D numerical simulations supported by DC experimental data are employed to quantify the impact of the key layout and technology parameters on the thermal resistance of state-of-the-art SiGe heterojunction bipolar transistors (HBTs) so as to define proper optimization criteria. The geometry parameters of a simple scalable model are optimized to describe the thermal resistance dependence upon emitter dimensions for the HBTs under analysis.
Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2010 IEEE; 11/2010
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ABSTRACT: A 160-GHz downconversion front-end for imaging arrays fabricated in a SiGe HBT technology is presented. The front-end features a fully differential architecture compatible with balanced on or off-chip antennas consisting of a three-stage LNA with 24 dB gain and Gilbert-cell mixer operating from -7dBm fundamental LO signal. The downconverter consumes 50 mA from a 3.3V supply and requires is 0.1 mm<sup>2</sup> die area (excl. pads) per channel. With an 160-GHz input signal and an IF frequency of 150 MHz, the implemented front-end yields a 27-dB conversion gain and a 7.4-dB/9.5-dB (without/with auxiliary on-chip input balun) system noise figure.
Microwave Conference (EuMC), 2010 European; 10/2010
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ABSTRACT: This paper presents a status of the HICUM model development activities (within the DOTFIVE project) for future technologies. Physics based scalable model libraries are realized for two of the most advanced SiGe:C HBT processes currently available. The parameter extraction methodology is described via two meaningful examples. Measurement and simulation comparisons are shown.
Microwave Integrated Circuits Conference (EuMIC), 2010 European; 10/2010
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ABSTRACT: Reliability performances of fully self aligned heterojunction bipolar transistors were investigated under high current and voltage stress conditions. We point out in this paper that generation-recombination traps induced by reverse bias stress can be repaired by forward bias. This is possible thanks to high enough device temperature (strong self-heating condition). Low frequency noise measurements and HICUM modelling of power dissipation refine this analysis. Finally, degradation of base-collector junction was investigated under mixed-mode stress and reveals a predominance of defects induced in the space charge area by impact ionization.
Reliability Physics Symposium, 2009 IEEE International; 05/2009
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ABSTRACT: mm-Wave applications claim for accurate and reliable device models for their very high frequency operation range. This is not possible without any representative measurement of the intrinsic device performances especially HF small-signal measurements. In this paper we determine major parasitic contributions of regular HF test structures. Parasitic investigation goes from the probes down to the transistor. Original dummies are described and HF/DC measurements are presented and analyzed. Based on this limited set of structures a scalable de-embedding approach is described. To account for DC/HF parasitics, a sub-circuit is proposed for modeling purpose.
Bipolar/BiCMOS Circuits and Technology Meeting, 2008. BCTM 2008. IEEE; 11/2008
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P. Chevalier,
B. Geynet,
B. Vandelle,
F. Brossard, F. Pourchon,
G. Avenier,
D. Gloria,
D. Dutartre,
S. Lepilliet,
G. Dambrine,
N. Zerounian,
K. Yau,
E. Laskin,
S.T. Nicolson,
S.P. Voinigescu,
A. Chantre
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ABSTRACT: In this paper we review a bit more than 10 years of SiGe BiCMOS technology development and present the best results published to date by the main contenders in the field. Next, with the support of recent results obtained at STMicroelectronics, we discuss the process optimization that led to further increase in the device operating speed. Finally, we present the characteristics of a 260GHz f<sub>T</sub>, 340GHz f<sub>max</sub> SiGe HBT technology along with recent circuit results demonstrated in this technology.
Device Research Conference, 2008; 07/2008
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ABSTRACT: This paper presents a detailed investigation of the dual base method for intrinsic and extrinsic HBT's base resistance extraction that is of utmost importance for process monitoring and device modeling purpose. Ring emitter test structures layout, dc measurement conditions, and extraction methodology have been improved to get reliable results. A particular attention has been drawn to the external base resistance extraction and the effect of parasitic resistances is highlighted. The method has been generalized for an extraction of the base resistance specific parameters using any number of geometries (widths and lengths) and therefore demonstrates the base resistance scalability. This method is applied to a ST state-of-art fully self aligned double poly BiCMOS SiGeC technology, and results are discussed.
IEEE Transactions on Semiconductor Manufacturing 06/2008; · 0.72 Impact Factor
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ABSTRACT: For device modelling purposes, the geometry dependence of the external collector resistance has been investigated. Firstly, the collector resistance is split into a perfectly 1D vertical resistance and a 2D horizontal contribution. Using specific test structures and DC measurements, geometry independent parameters are then extracted. An analytical scalable formula based on Fourier techniques finally computes both components for a given geometry by taking into account the current distribution in the horizontal layer. This new method is applied to a double poly BiCMOS technology and results are discussed.
Microelectronic Test Structures, 2007. ICMTS '07. IEEE International Conference on; 04/2007
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P. Chevalier,
D. Gloria,
P. Scheer,
S. Pruvost,
F. Gianesello, F. Pourchon,
P. Garcia,
J.-C. Vildeuil,
A. Chantre,
C. Garnier,
O. Noblanc,
S.P. Voinigescu,
T.O. Dickson,
E. Laskin,
S.T. Nicolson,
T. Chalvatzis,
K.H.K. Yau
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ABSTRACT: This paper presents the status of most advanced CMOS and BiCMOS technologies able to address very high-speed optical communications and millimeter-wave applications. The performance of active and passive devices available on bulk Si and high-resistivity SOI is reviewed and HF characteristics of state-of-the-art SiGe HBTs and MOSFETs are compared. The performance of building blocks designed in different CMOS and BiCMOS platforms are also presented. Finally, we conclude on the suitability of different Si technologies to address such high-frequency applications
Compound Semiconductor Integrated Circuit Symposium, 2006. CSIC 2006. IEEE; 12/2006
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P. Chevalier,
C. Raya,
B. Geynet, F. Pourchon,
F. Judong,
F. Saguin,
T. Schwartzmann,
R. Pantel,
B. Vandelle,
L. Rubaldo,
G. Avenier,
B. Barbalat,
A. Chantre
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ABSTRACT: This paper presents investigations led to simplify the collector module of SiGeC HBTs in order to reduce technology cost. Outcome of this work is an HBT featuring an all-implanted collector with record f<sub>T </sub> and f<sub>max</sub> (>250 GHz)
Bipolar/BiCMOS Circuits and Technology Meeting, 2006; 11/2006
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ABSTRACT: For process monitoring and device modeling, a new method to determine the different components of the base resistance of bipolar transistors has been developed. Dual base test structures have been improved to extract the sheet resistance value of each of these components using dc measurements. This method is applied to a state-of-art double poly ST BiCMOS technology, and results are discussed.
Microelectronic Test Structures, 2006. ICMTS 2006. IEEE International Conference on; 04/2006
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ABSTRACT: This paper describes a high frequency mismatch approach on BJT able to reach Ft=170GHz. All obtained results are complementary and all well linked with the mismatch extract from DC measurement and in good agreement with the model parameters. In order to extract these results, a new test structure and associated parameter extraction tool have been developed.
Microelectronic Test Structures, 2006. ICMTS 2006. IEEE International Conference on; 04/2006
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P. Chevalier,
D. Lagarde,
G. Avenier,
T. Schwartzmann,
B. Barbalat,
D. Lenoble,
J. Bustos, F. Pourchon,
F. Saguin,
B. Vandelle,
L. Rubaldo,
A. Chantre
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ABSTRACT: A low-cost SiGeC HBT module for bulk and SOI RFCMOS platforms is described. The device features an all-implanted collector and a novel fragmented emitter layout, and requires 4 masks only. Record performances are demonstrated, with cut-off frequencies f<sub>T</sub>/f <sub>max</sub> as large as 230/240GHz and 140/200GHz on bulk and thin SOI substrates respectively
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
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P. Chevalier,
C. Fellous,
L. Rubaldo, F. Pourchon,
S. Pruvost,
R. Beerkens,
F. Saguin,
N. Zerounian,
B. Barbalat,
S. Lepilliet,
D. Dutartre,
D. Celi,
I. Telliez,
D. Gloria,
F. Aniel,
F. Danneville,
A. Chantre
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ABSTRACT: This paper describes a 230-GHz self-aligned SiGeC heterojunction bipolar transistor developed for a 90-nm BiCMOS technology. The technical choices such as the selective epitaxial growth of the base and the use of an arsenic-doped monocrystalline emitter are presented and discussed with respect to BiCMOS performance objectives and integration constraints. DC and high-frequency device performances at room and cryogenic temperatures are given. HICUM model agreement with the measurements is also discussed. Finally, building blocks with state-of-the-art performances for a CMOS compatible technology are presented: A ring oscillator with a minimum stage delay of 4.4 ps and a 40-GHz low-noise amplifier with a noise figure of 3.9 dB and an associated gain of 9.2 dB were fabricated.
IEEE Journal of Solid-State Circuits 11/2005; · 3.23 Impact Factor
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ABSTRACT: This work presents a single-ended active mixer realized with a 0.13 μm BiCMOS SiGeC heterojunction bipolar transistor (HBT) technology. This mixer is designed to be integrated in a superheterodyne receiver for 40 GHz wireless communication systems. Local oscillator (LO) and RF signals are directly applied to the base of the HBT through two coupled lines. The mixer provides a down-conversion from 42 GHz to 2 GHz. The mixer exhibits a power conversion gain better than 2.4 dB and a measured double-sideband noise figure less than 8.3 dB for P<sub>LO</sub>=3 dBm (power of the local oscillator) under a global power consumption lower than 9.5 mW. This architecture exhibits good linearity performance with a measured IP<sub>1dB</sub> of about -7 dBm and an IIP3 of +4 dBm. The linear dynamic range for a 2 GHz system bandwidth is approximately 65 dB for P<sub>LO</sub>=+2 dBm and T<sub>0</sub>=290 K. The third order spurious free dynamic range is calculated to be better than 52 dB.
IEEE Microwave and Wireless Components Letters 09/2005; · 1.72 Impact Factor
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P Chevalier,
D Gloria,
P Scheer,
S Pruvost,
F Gianesello, F Pourchon,
P Garcia,
J.-C Vildeuil,
A Chantre,
C Garnier,
O Noblanc,
S P Voinigescu,
T O Dickson,
E Laskin,
S T Nicolson,
T Chalvatzis,
K H K Yau,
Edward S Rogers
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ABSTRACT: This paper presents the status of most advanced CMOS and BiCMOS technologies able to address very high-speed optical communications and millimeter-wave applications. The performance of active and passive devices available on bulk Si and high-resistivity SOI is reviewed and HF characteristics of state-of-the-art SiGe HBTs and MOSFETs are compared. The performance of building blocks designed in different CMOS and BiCMOS platforms are also presented. Finally, we conclude on the suitability of different Si technologies to address such high-frequency applications.
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ABSTRACT: V<sub>DD</sub> reduction in advanced CMOS IC's push for reduced temperature stability spread of bipolar based BGR. To achieve this goal, a reliable extraction methodology for I<sub>C</sub> temperature coefficient is detailed. Based on corner lot measurements, a worst-case bipolar model is built. Bandgap circuit measurements are finally compared to statistical simulations.
Bipolar/BiCMOS Circuits and Technology Meeting, 2007. BCTM '07. IEEE;
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ABSTRACT: Based on different geometries of bipolar transistors, a new scalable method to determine the parasitic capacitances is presented. The total capacitance measured from cold S parameters could be split in an area junction capacitance, a peripheral junction capacitance and a constant oxide contribution. This method is applied to a ST state-of-art fully self aligned double poly BiCMOS technology, and results are discussed.
Bipolar/BiCMOS Circuits and Technology Meeting, 2007. BCTM '07. IEEE;
