Are you S.L. Cho?

Claim your profile

Publications (6)0.79 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: A PRAM cell with great scalability and high speed operation capability with excellent reliability below 20nm technology was demonstrated. This has the meaning of the potential applicable to the technology area of scaling limitation of DRAM cell. We fabricated a confined PRAM cell with 7.5nm×17nm of below 4F<sup>2</sup>. In particular, Sb-rich Ge-Sb-Te phase change material was employed for high speed operation below 30nsec. The excellent writing endurance performance was predicted to maintain up to 6.5E15cycles by reset program energy acceleration. Its data retention was 4.5 years at 85°C which is enough for DRAM application.
    VLSI Technology (VLSIT), 2010 Symposium on; 07/2010
  • [Show abstract] [Hide abstract]
    ABSTRACT: We present a new-type confine structure within 7.5 nm width dash-contact for sub 20 nm generation PRAMs. Phase change material (PCM) by chemical vapor deposition (CVD) was perfectly filled in a 7.5 nm width dash-contact without void along with 30 nm depth. By adopting confined CVD-PCM, we were able to reduce the reset current below ~160 muA and to obtain high reliability. In addition, the programming time of dash-confined cell was much improved to 50 ns due to volume confinement of PCM cell. Consequently, we firstly demonstrate the high performance of the 7.5 nm width confined cell, which is the smallest size close to physical limit.
    Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
  • [Show abstract] [Hide abstract]
    ABSTRACT: first present a PRAM with confinement of chemically vapor deposited GeSbTe (CVD GST) within high aspect ratio 50 nm contact for sub 50 nm generation PRAMs. By adopting confined GST, we were able to reduce the reset current below ~260 muA and thermally stable CVD Ge<sub>2</sub>Sb<sub>2</sub>Te<sub>5</sub> compound having hexagonal phase was uniformly filled in a contact while maintaining constant composition along with 150 nm depth. Our results indicate that the confined cell structure of 50 nm contact is applicable to PRAM device below 50 nm design rule due to small GST size based on small contact and direct top electrode contact, reduced reset current, minimized etch damage, and low thermal disturbance effect.
    VLSI Technology, 2007 IEEE Symposium on; 07/2007
  • [Show abstract] [Hide abstract]
    ABSTRACT: We firstly fabricated on-axis confined structure and evaluated based on 64Mb PRAM with 0.12μm-CMOS technologies. Ge<sub>2</sub>Sb<sub>2</sub>Te <sub>5</sub> was confined within small pore, which resulted in low writing current of 0.4mA. The pore is on-axis with upper and lower contacts, which leads to good scalability of PRAM above 256Mb. The confined structure was relatively insensitive to small cell edge damage effect. The on-axis confined structure is a promising candidate for high density PRAM due to low writing current, good scalability, and insensitiveness to edge damage.
    VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
  • [Show abstract] [Hide abstract]
    ABSTRACT: Novel capacitor technologies for high density FRAM device with 0.18 μm D/R (design-rule) have been researched and developed. In order to realize the high-density FRAM device with 0.18 μm D/R, the PZT film was modified by changing Zr/Ti composition and by using PTO seeding layer. Therefore, the crystallization temperature of the PZT film could be successfully lowered to 550°C. The remnant polarization of PTO-used 100 nm thick PZT capacitors measured at 2.7 V was approximately 24 μC/cm, that is 30% higher than that of the PTO-unused PZT capacitors. Necessarily, as the PZT thickness and crystallization temperature are lowered, the thickness of bottom electrode can be reduced as well. Furthermore, by lowering the PZT crystallization temperature and by applying robust TiAlN oxidation barrier, low (300 Ω/contact) and stable contact resistance in a very small size of BC could be obtained. Finally, we successfully developed a capacitor stack height of 270 nm. The capacitor size was 0.26 × 0.44 μm and remnant polarization measured at 2.7 V was approximately 11 μC/cm.
    Ferroelectrics 01/2004; 303(1):15-23. · 0.42 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: Effects of the PbTiO 3 (PTO) seeding layer on lowering the PZT crystallization temperature and reducing the capacitor stack height, especially PZT thin film, were systematically investigated. For these purposes, PZT film was modified by using the PTO seeding layer. By using the PTO seeding layer; the crystallization temperature of the PZT film was successfully lowered to 550°C. And remanant polarization of PTO-used 100nm thick PZT capacitors measured at 3V was approximately 23 w C/cm 2 , that is 30% higher than that of the PTO-unused PZT capacitors. XRD analysis indicated that the use of the PTO seeding layer remarkably increased the relative intensity of (111) orientation. XRF studies showed that the atomic concentration ratio of Ti-to-Zr was increased by using PTO seeding layers. Necessarily, as the PZT thickness and crystallization temperature are lowered, the thickness of bottom electrode can be reduced as well. Finally, we successfully developed a capacitor stack height of below 400nm, which was composed of Ir/IrO 2 /PZT/Pt/IrO 2 . Furthemore, by lowering the PZT crystallization temperature, small (600 z /contact) and stable contact resistance in a very small size of BC could be obtained.
    Integrated Ferroelectrics 01/2002; 48(1):171-180. · 0.38 Impact Factor