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ABSTRACT: The asymmetric source/drain extension (ASDE) transistor can be a suitable option because of improved short channel effects in technology nodes beyond 32 nm. In this paper, we have analyzed the impact of asymmetric drain extension reduction on the device metrics, namely, gate-to-drain capacitance, drain current, subthreshold leakage, and gate tunneling leakage current. Also, analytical models have been developed to model the effect of the ASDE devices. Based on our proposed analytical model, SPICE-compatible transistor models have been developed to include the ASDE device structure as possible design options. With our SPICE-compatible transistor models, large-scale circuit simulation can be performed to evaluate the benefits and the overheads associated with the ASDE devices. It is observed from circuit simulations that there is an optimal drain extension length which is different from the source extension length. With the ASDE devices, the circuit power delay product can effectively be reduced by almost 35% with respect to the conventional symmetric devices.
IEEE Transactions on Electron Devices 05/2008; · 2.32 Impact Factor
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ABSTRACT: The inter-die and intra-die variations in process parameters (in particular, threshold voltage (Vt)) can lead to large number of failures in an SRAM array, thereby, degrading the design yield in nanometer technologies. To improve parametric yield of nano-scaled memories, different circuit and architectural level techniques can be used. In this paper, we first analyze and model different SRAM failures due to parameter variations, and discuss test methodologies to test for process variation induced failures. Next, we describe two different self-repairing techniques-at the circuit level, using adaptive body biasing and at the architecture level, using built-in-self-test (BIST), redundancy and address remapping. The discussed self-repair mechanisms can improve design yield much beyond what can be achieved using row/column redundancy and error correcting codes (ECC) alone.
Design and Diagnostics of Electronic Circuits and Systems, 2007. DDECS '07. IEEE; 05/2007
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20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India; 01/2007
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ABSTRACT: Super cut-off devices with sub-60mV/decade subthreshold swings have recently been demonstrated and being extensively studied. This paper presents a feasibility analysis of such tunneling devices for ultralow power subthreshold logic. Analysis shows that this device can deliver 800X higher performance (@iso-IOFF) compared to a MOSFET. The possible use of this device as a sleep transistor in conjunction with the regular Si MOSFET shows 2000X average improvement in leakage power compared to Si MOSFETs.
Low Power Electronics and Design, 2006. ISLPED'06. Proceedings of the 2006 International Symposium on; 11/2006
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ABSTRACT: The inter-die and intra-die variations in process parameters (in particular, threshold voltage (Vt)) can lead to large number of failures in an SRAM array, thereby, degrading the design yield in nanometer technologies. To improve parametric yield of nano-scaled memories, different circuit and architectural level techniques can be used. In this paper, we first analyze and model different SRAM failures due to parameter variations, and discuss test methodologies to test for process variation induced failures. Next, we describe two different self-repairing techniques-at the circuit level, using adaptive body biasing and at the architecture level, using built-in-self-test (BIST), redundancy and address remapping. The discussed self-repair mechanisms can improve design yield much beyond what can be achieved using row/column redundancy and error correcting codes (ECC) alone
Custom Integrated Circuits Conference, 2006. CICC '06. IEEE; 10/2006
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ABSTRACT: With transistor feature size scaling and higher integration density, power density has become a major problem. High power density results in elevated on chip temperature, which has significant impacts on power consumption and circuit reliability. In this work, we have presented a temperature adaptive design technique using a low overhead CMOS temperature sensor. We have shown that, by online monitoring of temperature, circuit power consumption can be adjusted adaptively so as to stabilize the chip temperature and achieve a robust design.
Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on; 04/2006
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Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006; 01/2006
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ABSTRACT: With increasing inter-die and intra-die parameter variations in sub-100-nm process technologies, new failure mechanisms are emerging in CMOS circuits. These failures lead to reduction in reliability of circuits, especially the area-constrained SRAM cells. In this paper, we have analyzed the emerging failure mechanisms in SRAM caches due to transistor V<sub>t</sub> variations, which results from process variations. Also we have proposed solutions to detect those failures efficiently. In particular, in this work, SRAM failure mechanisms under transistor V<sub>t</sub> variations are mapped to logic fault models. March test sequences have been optimized to address the emerging failure mechanisms with minimal overhead on test time. Moreover, we have proposed a design for test circuit to complement the March test sequence for at-speed testing of SRAMs. The proposed technique, referred as double sensing, can be used to test the stability of SRAM cells during read operations. Using the proposed March test sequence along with the double sensing technique, a test time reduction of 29% is achieved, compared to the existing test techniques with the same fault coverage. We have also demonstrated that double sensing can be used during SRAM normal operation for online detection and correction of any number of random read faults.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12/2005; 13(11):1286- 1295. · 1.22 Impact Factor
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ABSTRACT: Technology scaling has led to a reduction in the stored charge in SRAM memories. This has increased their vulnerability to soft errors. Conventional approaches to detect/correct soft errors, such as ECC, have limitation in the number of soft errors that can be tolerated. In this paper, we propose a soft error detection circuit which utilizes a current mirror to translate switching current pulses induced by soft errors into voltage pulses. This pulse is then sensed by a Schmitt trigger to generate an error signal. Our experimental results show that the proposed scheme is tolerant to process variation and results in low power overhead without significantly affecting performance.
Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on; 11/2005
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ABSTRACT: Large inter-die and intra-die process variations result in significant uncertainty in delay of circuits. Large delay variations may lead to parametric/functional failures. In this paper we propose a leakage-variation-tolerant online current monitor, namely leakage canceling current sensor, to detect completion of operations in logic blocks. The current monitor is applied to self timed logic to design process variation tolerant circuits. It is observed that, for self-timed circuits, the probability of functional failures can be reduced by 50% with no performance degradation and with same power consumption.
On-Line Testing Symposium, 2005. IOLTS 2005. 11th IEEE International; 08/2005
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ABSTRACT: In this paper, we have made a complete analysis of the emerging SRAM failure mechanisms due to process variations and mapped them to fault models. We have proposed two efficient test solutions for the process variation related failures in SRAM: (a) modification of March sequence, and (b) a low-overhead DFT circuit to complement the March test for an overall test time reduction of 29%, compared to the existing test technique with similar fault coverage.
VLSI Test Symposium, 2005. Proceedings. 23rd IEEE; 06/2005
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IEEE Trans. VLSI Syst. 01/2005; 13:1286-1295.
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Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005; 01/2005
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Qikai Chen
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ABSTRACT: As the CMOS technology continues to scale down to achieve higher performance, considerable power dissipation and reduced reliability in circuit functionality are emerging as major obstacles for circuit designs in the nanometer regime. In current micro-processor design, memory is an essential component. In this research, we have investigated techniques to reduce power consumption and to ensure robustness of memory circuits, in particular SRAM caches, from device, circuit and micro-architecture perspectives. From the device optimization perspective, a circuit-aware device design methodology is proposed for SRAM design. The proposed methodology has achieved significant reduction in SRAM cell leakage and access time, 11% and 7%, respectively, for a conventional 6T-SRAM. Also, we have modeled the impact of asymmetric device underlap on transistor characteristics. The benefits of using asymmetric underlap transistors in SRAM designs are evaluated. In addition, since parametric variations have significant impact on the stability of memory cells, the design and test of memories to ensure correct functionality is of considerable interests. In this work, from a circuit perspective, we have proposed a memory testing technique, which reduces the test application time by 29%. Also, we have explored a modeling technique to study the stability of memory cells under parametric variations. To further explore low power techniques in memory design, novel cache micro-architecture is investigated. In this research, an optimized micro-processor architecture based on dynamic loop detection directed cache (DLDDC ) is proposed. The proposed architecture takes advantages of the frequent executions of loops in program codes. Through dynamic loop detection, accurate way-prediction in set-associative data cache is achieved. The studies show that DLDDC can improve power dissipation in a micro-processor core by 12%, compared to a conventional architecture design. Furthermore, the overheads of DLDDC in terms of area and its own power consumption are negligible.
ETD Collection for Purdue University.
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ABSTRACT: In this paper, we propose a general Circuit-aware Device Design methodology, which can improve the overall circuit design by taking advantages of the individual circuit characters during the device design phase. The proposed methodology analytically derives the optimal device in terms of the pre-specified circuit quality factor. We applied the proposed methodology to SRAM design and achieved significant reduction in standby leakage and access time (11% and 7%, respectively, for conventional 6T-SRAM). Also, we observed that the optimal devices selected depend considerably on the applied circuit techniques. We believe that the proposed Circuit-aware Device Design methodology will be useful in the sub-90nm technology, where different leakage components (subthreshold, gate, and junction tunneling) are comparable in magnitude. Also, in this work, we have presented a design automation framework for SRAM, which is conventionally custom designed and optimized.
2008 Design, Automation and Test in Europe. 1:208.
