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ABSTRACT: We have demonstrated aggressively scaled high performance UTSOI replacement gate CMOS featuring a HfO<sub>2</sub>/TaN gate stack which achieves T<sub>inv</sub> of 17.5nm with greater than 100 times reduction in leakage compared to a SiON/poly-Si control sample. The atomic layer deposition process, used for the metal gate electrode material, enables the replacement gate structure to be robust at extremely small dimensions. An offset spacer together with the ultra-thin Si channel is used to demonstrate functional sub-25nm UTSOI replacement gate pFETs with high-k and metal gate for the first time. These results suggest that the replacement gate architecture is a viable option for future high performance CMOS technologies.
VLSI Technology, 2005. (VLSI-TSA-Tech). 2005 IEEE VLSI-TSA International Symposium on; 05/2005