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F. Arnaud,
A. Thean,
M. Eller,
M. Lipinski,
Y.W. Teh,
M. Ostermayr,
K. Kang,
N.S. Kim,
K. Ohuchi,
J.-P. Han, [......],
S. ElGhouli,
J. Bonnouvrier,
F. Matsuoka,
R. Lindsay, J. Sudijono,
F.S. Johnson,
J.H. Ku,
M. Sekine,
A. Steegen,
R. Sampson
[show abstract]
[hide abstract]
ABSTRACT: In this paper, we present a cost-effective 28 nm CMOS technology for low power (LP) applications based on a high-k, single-metal-gate-first architecture. We report raw gate densities up to 4200 kGate/mm<sup>2</sup>, and, using the ARM Cortex-R4F as a reference, we report achievement of an overall 2.4x area reduction in 28 nm from 45 nm technology. Our high-density SRAM bit-cell (area= 0.120mm<sup>2</sup>) has a demonstrated Static Noise Margin (SNM) of 213 mV at 1 V. Fully compatible with power/leakage management techniques intensively used in low power designs, the transistor drive currents are increased +35% & +10%, for nFET and pFET respectively, with respect to a 28 nm LP poly/SiON reference. Compatible with LP system-on-chip requirements, ultra low-cost, high performance analog devices are reported which leverage a dramatic improvement in matching factor (AVT~2mV.um) versus our previously-reported result. An optimized interconnection scheme based on Extreme Low k (ELK) dielectric (k~2.4) and advanced metallization allows high density wiring with competitive R-C versus our previous technology.
Electron Devices Meeting (IEDM), 2009 IEEE International; 01/2010
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F. Chen,
M. Shinosky,
B. Li,
J. Gambino,
S. Mongeon,
P. Pokrinchak,
J. Aitken,
D. Badami,
M. Angyal,
R. Achanta,
G. Bonilla,
G. Yang,
P. Liu,
K. Li, J. Sudijono,
Y. Tan,
T.J. Tang,
C. Child
[show abstract]
[hide abstract]
ABSTRACT: During technology development, the study of ultra low-k (ULK) TDDB is important for assuring robust reliability. As the technology advances, several critical ULK TDDB issues were faced for the first time and needed to be addressed. First, the increase of ULK leakage current noise level induced by soft breakdown during stress was observed. Second, it was found that ULK had lower field acceleration than dense low-k. Such process and material dependences of ULK TDDB kinetics were investigated, and an optimal process to improve ULK voltage acceleration was identified. Last, as the reliability margin for ULK TDDB of via-related structures is greatly reduced at advanced CMOS technologies, a systematic study of via TDDB regarding area scaling and test structure design was conducted. It was found that only a portion of the total vias possibly determines the low-k via TDDB. A new ldquofatalrdquo via ratio concept is introduced to replace the as-designed area ratio for TDDB area scaling in structures with vias, and a methodology called shift and compare (S&C) is proposed to determine the ldquofatalrdquo via ratio.
Reliability Physics Symposium, 2009 IEEE International; 05/2009
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H.S. Yang,
R. Wong,
R. Hasumi,
Y. Gao,
N.S. Kim,
D.H. Lee,
S. Badrudduza,
D. Nair,
M. Ostermayr,
H. Kang, [......],
S. Samavedam,
D. Jaeger,
C.V. Baiocco,
M. Sherony,
M. Khare,
C. Lage,
J. Pape, J. Sudijono,
A.L. Steegen,
S. Stiffler
[show abstract]
[hide abstract]
ABSTRACT: This paper describes SRAM scaling for 32 nm low power bulk technology, enabled by high-K metal gate process, down to 0.149 mum<sup>2</sup> and 0.124 mum<sup>2</sup>. SRAM access stability and write margin are significantly improved through a 50% Vt mismatch reduction, thanks to HK-MG T<sub>inv</sub> scaling. Cell read current is increased by 70% over Poly-SiON process. Ultra dense cell process window is expanded with optimized contact process. A dual-ground write assist option can additionally enable ultra dense 0.124 mum<sup>2</sup> cell to meet low power application requirements.
Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
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F. Arnaud,
J. Liu,
Y.M. Lee,
K.Y. Lim,
S. Kohler,
J. Chen,
B.K. Moon,
C.W. Lai,
M. Lipinski,
L. Sang, [......],
D.V. Coolbaugh,
H.W. Kim,
Y.C. Ee, J. Sudijono,
A. Thean,
M. Sherony,
S. Samavedam,
M. Khare,
C. Goldberg,
A. Steegen
[show abstract]
[hide abstract]
ABSTRACT: This paper presents for the first time a full 32 nm CMOS technology for high data rate and low operating power applications using a conventional high-k with single metal gate stack. High speed digital transistors are demonstrated 22% delay reduction for ring oscillator (RO) at same power versus previous SiON technology. Significant matching factor (A<sub>VT</sub>) improvement (A<sub>VT</sub>~2.8 mV.um) and low 1/f noise aligned with poly SiON are reported. Excellent static noise margin (SNM) of 213 mV has been achieved at low voltage for a high density 0.157 um<sup>2</sup> SRAM cell. Hierarchical BEOL based on extreme low k (ELK) dielectric (k~2.4) is presented allowing high density wiring with low RC delay. Reliability criteria have been met for hot carrier injection (HCI), gate dielectric break-down (TDDB) and bias temperature instability (BTI) extracted at 125degC.
Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
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J. Yuan,
V. Chan,
M. Eller,
N. Rovedo,
H.K. Lee,
Y. Gao,
V. Sardesai,
N. Kanike,
V. Vidya,
O. Kwon, [......],
O. Gluschenkov,
M.R. Visokay,
C. Radens,
S. Deshpande,
H. Shang,
Y. Li,
N. Cave, J. Sudijono,
J. Ku,
R. Divakaruni
[show abstract]
[hide abstract]
ABSTRACT: This paper presents a cost-effective low power 45 nm bulk technology platform, primarily designed to serve the wireless multimedia and consumer electronics need. This technology platform features carbon co-IIP in the nMOS halo, laser annealing scheme, stress liner on the 45°-rotated wafer (<100>) for process simplicity to achieve high device performance and low leakage together. Drive current as high as 650/320 uA/um at Ioff of 0.5 nA/um with Vdd=1.1V has been achieved for both NMOS and PMOS respectively. Ring oscillator speed (FO=1) has been boosted up by 30% with the device optimization. SRAM Vt mismatch is also improved by 10% with carbon co-IIP with good SRAM characteristics and low leakage current in 0.299 um<sub>2</sub> cell.
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on; 11/2008
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X. Chen,
S. Samavedam,
V. Narayanan,
K. Stein,
C. Hobbs,
C. Baiocco,
W. Li,
D. Jaeger,
M. Zaleski,
H.S. Yang, [......],
S. Pandey,
D. Tekleab,
A. Thean,
M. Sherony,
C. Lage, J. Sudijono,
R. Lindsay,
J.H. Ku,
M. Khare,
A. Steegen
[show abstract]
[hide abstract]
ABSTRACT: For the first time, we have demonstrated a 32 nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mum<sup>2</sup>. Record NMOS/PMOS drive currents of 1000/575 muA/mum, respectively, have been achieved at 1 nA/mum off-current and 1.1 V V<sub>dd</sub> with a low cost process. With this high performance transistor, V<sub>dd</sub> can be further scaled to 1.0 V for active power reduction. Through aggressive EOT scaling and band-edge work-function metal gate stacks, appropriate Vts and superior short channel control has been achieved for both NMOS and PMOS at L<sub>gate</sub> = 30 nm. Compared to SiON-Poly, 30% RO delay reduction has been demonstrated with HK-MG devices. 40% Vt mismatch reduction has been shown with the Tinv scaling. Furthermore, it has been shown that the 1/f noise and transistor reliability exceed the technology requirements.
VLSI Technology, 2008 Symposium on; 07/2008
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S.S. Tan,
S Fang,
J Yuan,
L Zhao,
Y M Lee,
J J Kim,
R Robinson,
J Yan,
J Park,
M. Belyansky, [......],
S D Kim,
N. Rovedo,
H Shang,
H. Ng,
Y Li, J. Sudijono,
E. Quek,
S. Chu,
R. Divakaruni,
S. Iyer
[show abstract]
[hide abstract]
ABSTRACT: A novel low cost technique to improve device performance by enhanced stress proximity technique (eSPT) with recessed S/D (ReSD) has been demonstrated for the first time. pFET performance improvement of 40% was demonstrated with eSPT. pFET performance with Ion of 520 uA/um at Ioff of InA/um was achieved with the low cost processes. With optimized eSPT, 15% improvement in ring delay has been demonstrated.
VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on; 05/2008
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Z. Luo,
N. Rovedo,
S. Ong,
B. Phoong,
M. Eller,
H. Utomo,
C. Ryou,
H. Wang,
R. Stierstorfer,
L. Clevenger, [......],
S. Lee,
A. Vayshenker,
Z. Yang,
C. Tian,
H. Ng,
H. Shang,
M. Hierlemann,
J. Ku, J. Sudijono,
M. Ieong
[show abstract]
[hide abstract]
ABSTRACT: An aggressively scaled high performance 45 nm bulk CMOS technology targeting graphic, gaming, wireless and digital home applications is presented. Through innovative utilization and integration of advanced stressors, thermal processes and other technology elements, at aggressively scaled 45 nm design ground rules, core NFET and PFET realized world leading drive currents of 1150 and 785 uA/um at 100 nA/um off current at IV, respectively. In addition to the high performance transistors, an ultra low-k back-end dielectric (k=2.4) significantly lowers wiring delay. In this technology, CMOS transistors with multiple-oxide thicknesses are supported for low leakage and I/O operations, and competitive SRAM is offered.
VLSI Technology, 2007 IEEE Symposium on; 07/2007
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J.P. Han,
H. Utomo,
L.W. Teo,
N. Rovedo,
Z. Luo,
R. Krishnasamy,
R. Stierstorfer,
Y.F. Chong,
S. Fang,
H. Ng, [......],
R. Loesing,
S.D. Kim,
R. Lindsay,
G. Chiulli,
R. Amos,
M. Hierlemann,
D. Shum,
J.H. Ku, J. Sudijono,
M. Ieong
[show abstract]
[hide abstract]
ABSTRACT: We present an advanced CMOS integration scheme based on embedded SiGe (eSiGe) with a novel graded germanium process. The retention of channel strain enabled a pFET performance gain of 15% over a non-graded eSiGe control. When combined with a compressive stress liner (CSL), the pFET drive current reached 770muA/mum at I<sub>off</sub> = 100nA/mum with V<sub>DD</sub> = 1V. Competitive nFET performance was maintained. Parasitics such as silicide and junction characteristics were not degraded
Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
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[show abstract]
[hide abstract]
ABSTRACT: This work investigates the impact of negative bias temperature instability (NBTI) on the SRAM cell stability. As proposed by C. Wang et al., the stability of an SRAM cell can be determined by the peak current (I<sub>CRIT</sub>) of the "N curve". In our experiments a typical NBTI stress was applied to one of the two pull up transistors part of an SRAM cell designed by using an advanced submicron CMOS technology. Both the mean and variance of the pMOSFET threshold voltage shift in saturation (DeltaVt<sub>SAT</sub>) and the corresponding values of the I<sub>CRIT </sub> shifts (DeltaI<sub>CRIT</sub>) were measured. An experimental correlation between the means and the variances of both parameters shifts was established and found consistent with the predicted simulated values in the case of I<sub>CRIT</sub> is degrading by only NBTI aging of the one or both pull up transistors. These results allow us to observe the direct impact of the NBTI shift of a pMOSFET transistor in a SRAM cell and the corresponding reduction to the static noise margin. In addition we propose, for the first time, a methodology to define a pMOSFET device NBTI target directly related to the SRAM cell stability and its dependence on SRAM design and the adopted CMOS technology. It is found that a more appropriate SRAM stability sensitive pMOSFET NBTI Vt <sub>SAT</sub> target cannot be limited to the Vt<sub>SAT</sub> mean shift, but needs as well a quantification of the allowed variance and initial SRAM I<sub>CRIT</sub> distribution
Reliability Physics Symposium Proceedings, 2006. 44th Annual., IEEE International; 04/2006
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K.Y. Lim,
V. Chan,
R. Rengarajan,
H K Lee,
N. Rovedo,
E.H. Lim,
S Yang,
F. Jamin,
P Nguyen,
W Lin,
C.W. Lai,
Y.W. Teh,
J Lee,
L. Kim,
Z Luo,
H. Ng, J. Sudijono,
C. Wann,
I Yang
[show abstract]
[hide abstract]
ABSTRACT: In this paper, a study on middle-of-line (MOL) process on transistor performance and reliability was presented based on 300mm experimental data. The major MOL parameters that are affecting device performance and reliability are MOL thermal expense and mechanical stress from contact etches stop nitride liner. Based on the study, we had developed a robust 45nm gate-length CMOSFET for 90nm node high performance application. Aggressive gate length and gate dielectric scaling along with optimized MOL engineering has proven high performance devices similar to 65nm node CMOSFET (Nakahara et al., 2003).
Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European; 10/2005
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C. Wann,
R. Wong,
D.J. Frank,
R. Mann,
Shang-Bin Ko,
P. Croce,
D. Lea,
D. Hoyniak,
Yoo-Mi Lee,
J. Toomey,
M. Weybright, J. Sudijono
[show abstract]
[hide abstract]
ABSTRACT: SRAM stability during word line disturb (access disturb) is becoming a key constraint for V<sub>DD</sub> scaling (Burnett, 1994). In this paper we present a design methodology for SRAM stability during access disturb. In this methodology, the SRAM access disturb margin (ADM) is defined as the ratio of the magnitude of the critical current to maintain SRAM stability (I<sub>CRIT</sub>) to the sigma of I<sub>CRIT</sub>. Using ADM as a figure of merit, this methodology enables one to project the cell stability margin due to process variations, e.g. V<sub>T</sub> variation, during design of a SRAM cell. Using statistical analysis, the required stability margin for an application requirement such as array size and available redundancy can be estimated. Direct cell probing and array test can be used to verify that the stability target is met.
VLSI Technology, 2005. (VLSI-TSA-Tech). 2005 IEEE VLSI-TSA International Symposium on; 05/2005
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H.S. Yang,
R. Malik,
S. Narasimha,
Y. Li,
R. Divakaruni,
P. Agnello,
S. Allen,
A. Antreasyan,
J.C. Arnold,
K. Bandy, [......],
R. van Bentum,
G. Grasshoff,
C. Schwan,
E. Ehrichs,
S. Goad,
J. Buller,
S. Krishnan,
D. Greenlaw,
M. Raab,
N. Kepler
[show abstract]
[hide abstract]
ABSTRACT: For the first time, tensile and compressively stressed nitride contact liners have been simultaneously incorporated into a high performance CMOS flow. This dual stress liner (DSL) approach results in NFET/PFET effective drive current enhancement of 15%/32% and saturated drive current enhancement of 11%/20%. Significant hole mobility enhancement of 60% is achieved without using SiGe. Inverter ring oscillator delay is reduced by 24% with DSL. Overall yield for the DSL process is comparable to that of a similar technology without DSL. Single and multi-core SOI microprocessors are being manufactured using the DSL process in multiple, high-volume fabrication facilities.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
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Z. Luo,
A. Steegen,
M. Eller,
R. Mann,
C. Baiocco,
P. Nguyen,
L. Kim,
M. Hoinkis,
V. Ku,
V. Klee, [......],
Y. Lin,
K. Lee,
H. Zhu,
M. Weybright,
R. Rengarajan,
J. Ku,
T. Schiml, J. Sudijono,
I. Yang,
C. Wann
[show abstract]
[hide abstract]
ABSTRACT: This paper reports a cutting-edge 65nm CMOS technology featuring high performance and low power CMOS devices for both general and low power applications. Utilizing plasma nitrided gate oxide, off-set and slim spacers, advanced co-implants, NiSi and low temperature MOL process, well designed NMOSFET and PMOSFET achieved significant improvement from the previous generation, especially PMOSFET has demonstrated an astonishing 35 % performance enhancement from the previous technology node
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 02/2004
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[show abstract]
[hide abstract]
ABSTRACT: We studied and compared the extent of plasma induced damage from
high density plasma (HDP) undoped silicate glass (USG) and fluorinated
silicate glass (FSG) deposition on 0.18 μm transistors. Our results
show that the plasma-induced damage from HDP FSG is greater than that
from HDP USG. We have developed a novel integration scheme that is
effective in reducing the damage from HDP FSG down to levels comparable
to that of USG
Plasma Process-Induced Damage, 2000 5th International Symposium on; 02/2000
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[show abstract]
[hide abstract]
ABSTRACT: Scanning tunneling microscopy studies have been performed on GaAs homoepitaxial films grown by molecular‐beam epitaxy. After an initial transient regime, indicated by reflection high‐energy electron diffraction oscillations, the system evolves to a dynamical steady state. This state is characterized by a constant step density and as such the growth mode can be termed generalized step flow.
Applied Physics Letters 02/1994; · 3.84 Impact Factor
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[show abstract]
[hide abstract]
ABSTRACT: Scanning tunneling microscopy studies have been performed on GaAs(001) homoepitaxial films. By quenching the growth, we are able to image the surface as it appeared during deposition. Images from the early stage of growth show that the morphology oscillates between one with two‐dimensional islands and flat terraces. It is noted that there is a correspondence between the surface step density and reflection high‐energy electron diffraction specular intensity. In addition, depending upon the buffer layer preparation prior to the desired growth there is a significant difference in the surface morphology. Two processing methods are presented that produce recovered surfaces with either a high or low step density. Possible mechanism will be discussed.
Journal of vacuum science & technology. B, Microelectronics and nanometer structures: processing, measurement, and phenomena: an official journal of the American Vacuum Society 06/1993; · 1.34 Impact Factor
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[show abstract]
[hide abstract]
ABSTRACT: Scanning tunneling microscopy studies have been performed on GaAs homoepitaxial films grown by molecular-beam epitaxy. Images show that in the earliest stages of deposition the morphology oscillates between one with two-dimensional islands and flat terraces. After the initial transient regime, the system evolves to a dynamical steady state. This state is characterized by a constant step density and as such the growth mode can be termed step flow. Comparison with RHEED shows that there is a direct correspondence between the surface step density and the RHEED specular intensity. Furthermore, thick films (up to 1450 monolayers) display a constant or slowly increasing surface roughness consistent with long adatom diffusion lengths and limited upward diffusion.
Surface Science.
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[show abstract]
[hide abstract]
ABSTRACT: Scanning tunneling microscopy studies have been performed on GaAs homoepitaxial films grown by molecular-beam epitaxy. Images show that in the earliest stages of deposition the morphology oscillates between one with two-dimensional islands and flat terraces. After the initial transient regime, the system evolves to a dynamical steady state. This state is characterized by a constant step density and as such the grown mode can be termed step flow. Comparison with reflection high-energy electron-diffraction (RHEED) shows that there is a direct correspondence between the surface step density and the RHEED specular intensity. Thick films (up to 1450 monolayers) display a slowly-increasing surface roughness. Analysis of the scaling properties and comparison with theories of film growth will be made.
Solid-State Electronics.
-
X. Chen,
S. Fang,
W. Gao,
T. Dyer,
Y.W. Teh,
S.S. Tan,
Y. Ko,
C. Baiocco,
A. Ajmera,
J. Park, [......],
R. Amos,
H. Ng,
M. Hierlemann,
D. Coolbough,
A. Steegen,
I. Yang, J. Sudijono,
T. Schiml,
J.H. Ku,
C. Davis
[show abstract]
[hide abstract]
ABSTRACT: Integration of stress proximity technique (SPT) and dual stress liners (DSL) has been demonstrated for the first time. The proximity of stress liner is enhanced by spacer removal after salicidation and before the DSL process. It maximizes the strain transfer from nitride liner to the channel. PFET drive current improvements of 20% for isolated and 28% for nested poly gate pitch devices have been achieved with SPT. Leading edge PFET I<sub>on</sub>=660muA/mum at I<sub>off</sub>=100nA/mum at 1V V<sub>dd</sub> operation is demonstrated without using embedded SiGe junctions. Inverter ring oscillator delay is reduced by 15% with SPT
VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on;
