S. Ramesh

Publications (2)0 Total impact

• Article: Scenario-Based Specification of Automotive Requirements With Quantitative Constraints and Synthesis of SL/SF Monitors

  S. Arora, A.A. Gadkari, S. Ramesh
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  ABSTRACT: Requirements of embedded systems often describe the system behavior with quantitative constraints over parameters such as timing, memory, and other resources. In this letter, we present a visual language suited for scenario-based specification of requirements with quantitative constraints. Our language, known as event sequence charts with quantitative constraints (ESC-QC), is inspired by message sequence charts (MSC) and its variants. We introduce ESC-QC notations through an example from automotive requirements and then describe the formal syntax and semantics. Besides being useful for formal documentation and analysis of system requirements, ESC-QC specifications can be translated into monitors and used for run-time verification of designs. In automotive systems Simulink/Stateflow (SL/SF) is widely used for design of control systems. We have developed an algorithm for automatic synthesis of SL/SF monitors from ESC-QC specifications. We have used this algorithm for generating monitors for verification of controller models from active safety and body control applications.
  IEEE embedded systems letters 07/2011;
• Source

  Available from: arxiv.org

  Conference Proceeding: Automated synthesis of assertion monitors using visual specifications

  A.A. Gadkari, S. Ramesh
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  ABSTRACT: Automated synthesis of monitors from high-level properties plays a significant role in assertion-based verification. We present a methodology to synthesize assertion monitors from visual specifications given in CESC (Clocked Event Sequence Chart). CESC is a visual language designed for specifying system level interactions involving single and multiple clock domains. It has well-defined graphical and textual syntax and formal semantics based on a synchronous language paradigm enabling formal analysis of specifications. We provide an overview of the CESC language with a few illustrative examples. The algorithm for automated synthesis of assertion monitors from CESC specifications is described. A few examples from standard bus protocols (OCP-IP and AMBA) are presented to demonstrate the application of the monitor synthesis algorithm.
  Design, Automation and Test in Europe, 2005. Proceedings; 04/2005