Publications (4)0 Total impact
Conference Proceeding: Bended Gate-All-Around Nanowire MOSFET: a device with enhanced carrier mobility due to oxidation-induced tensile stress[show abstract] [hide abstract]
ABSTRACT: In this paper we investigate the mobility enhancement due to strain in bended NW MOSFETs. Stress of 200 MPa to 2 GPa, induced by thermal oxidation, is measured in suspended NW FETs by Raman spectroscopy. Mobility enhancement of more than 100% is observed. Performance gain of bended compared to non-bended structures is most pronounced in low field conditions and at low temperatures.Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
Article: Silicon nanowires with lateral uniaxial tensile stress profiles for high electron mobility gate-all-around MOSFETs[show abstract] [hide abstract]
ABSTRACT: In this work we present for the first time correlation of lateral uniaxial tensile strain and I–V characteristics of GAA Si NW n-MOSFET, all measured on the same device. Micro-Raman spectroscopy is employed for direct strain measurement on devices to exploit the main sources of process-induced strain, found to be accumulation of mechanical potential energy in the Si NWs during local oxidation and releasing it in the form of local lateral uniaxial tensile stress in the Si NW by out-of-plane mechanical buckling as well as lateral in-plane elongation during stripping the hard mask and the grown oxide. A triangular GAA Si NW with 0.6 GPa peak of lateral uniaxial tensile stress, fabricated using this bulk top-down technology, exhibits promising improvements e.g. of the normalized drain current (ID/Weff) up to 38%, of the transconductance (gm/Weff) up to 50%, of the low field mobility by 53% with a peak of 64% in the peak stress region, compared to a reference device. The mobility extraction originally takes into account the measured strain profile in the channel.
Article: Investigation of Strain Profile Optimization in Gate-All-Around Suspended Silicon Nanowire FET
Article: Optimization of the channel lateral strain profile for improved performance of multi-gate MOSFETs[show abstract] [hide abstract]
ABSTRACT: We report for the first time the optimization of the channel lateral strain profile as a new technological booster for improved performance of multi-gate n-channel MOSFET. We find that quasi-uniform or flat-Gaussian-close-to-the-drain profiles are optimum for the Ion boosting of sub-50nm scaled MOSFETs, while the penalty on Ioff and subthreshold slope is minimum. The reported predictions use realistic lateral uniaxial strain profiles, with peaks up to few GPa's and average values of hundreds of MPa's. ©2009 IEEE.