S.H. Olsen

Newcastle University, Newcastle-on-Tyne, England, United Kingdom

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Publications (87)121.35 Total impact

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    ABSTRACT: Strained silicon is used to enhance performance in state-of-the-art CMOS. Under device operating conditions, the effect of strain is to reduce the carrier scattering at the channel by a smoother semiconductor surface. This has never been completely understood. This paper gives first evidence of the variation in surface roughness under realistic strained conditions. At the nanoscale, the SiO2/Si interface roughness is dependent on the scale of observation (self-affinity). To date, there is no experimental study of the SiO2/Si interface roughness scaling with strain. This work presents the effect of uniaxial and biaxial strains on the surface roughness of strained silicon-on-insulator films and wires using atomic force microscopy. Levels of strain ranging from 0% to 2.3%, encompassing those used in present CMOS devices have been investigated. It is shown that the silicon surface is affected by uniaxial and biaxial strains differently. Three surface roughness parameters have been analyzed: root mean square roughness, correlation length, and the Hurst exponent, which is used to describe the scaling behavior of a self-affine surface. The results show that the root mean square roughness decreases (up to ∼40%) with increasing tensile strain, whereas the correlation length increases (up to ∼63 nm/%) with increasing tensile strain. The Hurst exponent also varies with strain and with the undulation wavelength regime (between ∼0.8 and 0.2). This dependency explains why some models used to determine the carrier mobility from experiments fit the data better with a Gaussian form, whereas other models fit the data better with an exponential form.
    Journal of Applied Physics 09/2014; 116(12):124503-124503-12. · 2.19 Impact Factor
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    ABSTRACT: Pulsed I-V and AC conductance or RF characterization techniques, within the time and the frequency domain, respectively, represent two approaches for evaluating self-heating in MOSFETs. In this paper, these methods are compared. Advantages and limitations of each technique are discussed and experimentally verified in silicon-on-insulator (SOI) MOSFETs. It is demonstrated that RF technique and the pulsed I-V hot chuck method agree well for the studied 130-nm-node partially depleted SOI devices. Applicability of the techniques for advanced technologies is discussed.
    IEEE Transactions on Electron Devices 06/2013; 60(6):1844-1851. · 2.36 Impact Factor
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    ABSTRACT: In this work we investigate the effect of ground plane (GP) on analog figures of merit (FoM) of ultra-thin body and thin buried oxide (UTBB) SOI MOSFETs. Based on experimental devices, both n- and p-type GP configurations are considered and compared with standard no-GP substrates. In a standard single-gate (SG) regime, the effect of GP implementation on analog FoM (related to slightly higher body factor and improved gate-to-channel coupling) is negligible. Moreover, p-GP implementation allows higher intrinsic gain at high frequency compared with no-GP and n-GP substrates. Furthermore, we demonstrate that application of an asymmetric double-gate (ADG) (i.e. front-gate to back-gate/substrate connection) regime allows better control of short-channel effects in terms of drain induced barrier lowering, subthreshold slope and threshold voltage control, due to improved gate(s)-to-channel coupling. Application of an ADG mode is shown to enhance analog FoM such as transconductance, drive current and intrinsic gain of UTBB SOI MOSFETs. Finally, simulations predict that improvements of analog FoM provided by ADG mode can be obtained in the whole dynamic operation range. Moreover, ADG mode provides elimination of the high-frequency substrate coupling effects.
    Solid-State Electronics 01/2013; 90:56–64. · 1.51 Impact Factor
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    ABSTRACT: In this work, strain in silicon free standing beams loaded in uniaxial tension is experimentally and theoretically investigated for strain values ranging from 0 to 3.6%. The fabrication method allows multiple geometries (and thus strain values) to be processed simultaneously on the same wafer while being studied independently. An excellent agreement of strain determined by two non-destructive characterization techniques, Raman spectroscopy and mechanical displacement using scanning electron microscopy (SEM) markers, is found for all the sample lengths and widths. The measured data also show good agreement with theoretical predictions of strain based upon continuum mechanical considerations, giving validity to both measurement techniques for the entire range of strain values. The dependence of Young's modulus and fracture strain on size has also been analyzed. The Young's modulus is determined using SEM and compared with that obtained by resonance-based methods. Both methods produced a Young's modulus value close to that of bulk silicon with values obtained by resonance-based methods being slightly lower. Fracture strain is analyzed in 40 sets of samples with different beam geometries, yielding values up to 3.6%. The increase in fracture strain with decreasing beam width is compared with previous reports. Finally, the role of the surface on the mechanical properties is analyzed using UV and visible lasers having different penetration depths in silicon. The observed dependence of Raman shift on laser wavelength is used to assess the thermal conductivity of deformed silicon.
    Journal of Applied Physics 12/2012; 112(11). · 2.19 Impact Factor
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    Solid-State Electronics 04/2012; · 1.51 Impact Factor
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    ABSTRACT: Nanomechanical testing of silicon is primarily motivated toward characterizing scale effects on the mechanical behavior. “Defect-free” nanoscale silicon additionally offers a road to large deformation permitting the investigation of transport characteristics and surface instabilities of a significantly perturbed atomic arrangement. The need for developing simple and generic characterization tools to deform free-standing silicon beams down to the nanometer scale, sufficiently equipped to investigate both the mechanical properties and the carrier transport under large strains, has been met in this research through the design of a versatile lab-on-chip. The original on-chip characterization technique has been applied to monocrystalline Si beams produced from Silicon-on-Insulator wafers. The Young’s modulus was observed to decrease from 160 GPa down to 108 GPa when varying the thickness from 200 down to 50 nm. The fracture strain increases when decreasing the volume of the test specimen to reach 5% in the smallest samples. Additionally, atomic force microscope-based characterizations reveal that the surface roughness decreases by a factor of 5 when deforming by 2% the Si specimen. Proof of concept transport measurements were also performed under deformation up till 3.5% on 40-nm-thick lightly p-doped silicon beams.
    Journal of Materials Research. 02/2012; 27(03).
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    ABSTRACT: In this work UTBB devices with different BOX thicknesses of 10 and 25 nm are compared in terms of self-heating (SH) effect Different approaches of SH characterisation are assessed. Strengths and weaknesses of every extraction technique when applied to advanced UTBB MOSFETs are discussed. We show that while thermal effects are important even in devices with ultra-thin BOX, the resulting drain current degradation is not severe and is not considerably affected by BOX thickening from 10 to 25 nm. The main SH-related issue is output conductance degradation, which is of great importance for analogue applications.
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    ABSTRACT: Surface roughness in uniaxially loaded strained Si has been studied experimentally using high-resolution atomic force microscopy and a microelectromechanical systems-based on-chip loading device. A reduction in rms roughness from 0.29 nm to 0.07 nm has been identified as strain increases from 0 to 2.8% (stress from 0 to 4.9 GPa). The correlation length of the roughness, also known to affect carrier mobility, increases with increasing strain up to 1.7% before reducing at larger levels of strain. These results partly explain the high-field mobility observed in strained Si, indicating that a modified correlation length should also be considered in transport modelling of strained Si.
    Applied Physics Letters 12/2011; 99(24). · 3.52 Impact Factor
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    ABSTRACT: Epitaxial growth of strained layers used for highspeed electronic devices can induce surface roughness, which impacts gate dielectric properties. To precisely understand the effect of roughness on the quality and reliability of dielectrics, high-spatial-resolution characterization techniques are required. In this paper, we use conductive atomic force microscopy (C-AFM) to enable gate leakage analysis at the nanoscale in fully processed high-mobility strained Si MOSFETs. This is achieved by the selective removal of the gate from the dielectric, followed by nanoscale C-AFM analysis of the dielectric surface. A Hertzian contact model has been used to account for the tip-sample contact area in order to extract the current density. The techniques are applied to strained Si and bulk Si devices with different surface morphologies and macroscopic electrical data. The results suggest that materials exhibiting long-scale surface undulations are prone to degraded dielectric properties because gate leakage is increased at the highly sloped regions of the roughness. This effect is masked during conventional macroscopic electrical measurements. The increasing leakage also leads to compromised dielectric reliability. Dielectric lifetime was assessed through device stressing and has been found to be related to the level of surface roughness induced by the underlying substrate.
    IEEE Transactions on Electron Devices 12/2011; · 2.36 Impact Factor
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    ABSTRACT: Multigate semiconductor devices are celebrated for improved electrostatic control and reduced short-channel effects. However, nonplanar architectures suffer from increases of access resistances and capacitances, as well as self-heating effects due to confinement and increased phonon boundary scattering. In silicon-on-insulator (SOI) technology, the self-heating effects are aggravated by the presence of a thick buried oxide with low thermal conductivity, which prevents effective heat removal from the device active region to the Si substrate. Due to the shrinking of device dimensions in the nanometer scale, the thermal time constant that characterizes the dynamic self-heating is significantly reduced, and radio frequency extraction techniques are needed. The dynamic self-heating effect is characterized in n-channel SOI FinFETs, and the dependence of thermal resistance on FinFET geometry is discussed. It is experimentally confirmed that the fin width and the number of parallel fins are the most important parameters for thermal management in FinFETs, whereas fin spacing plays a less significant role.
    IEEE Transactions on Electron Devices 11/2011; · 2.36 Impact Factor
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    ABSTRACT: Self-heating and substrate effects are discussed and qualitatively compared in the ultra-thin body ultra-thin BOX (UTB<sup>2</sup>) devices without a ground plane. Ultra-thin body is aggravating thermal properties of the devices due to the interface effects. Ultra-thin BOX (10 nm) improves heat dissipation from the channel to the bulk silicon substrate but also results in strongly pronounced substrate effects. It is observed that output conductance degradation in the UTB<sup>2</sup> devices due to the substrate effects can be as strong as degradation due to the self-heating.
    Ultimate Integration on Silicon (ULIS), 2011 12th International Conference on; 04/2011
  • S. Makovejev, S. Olsen, J. Raskin
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    ABSTRACT: Dynamic self-heating effect is characterised in n-channel FinFETs on Silicon-on-Insulator (SOI) platform. RF extraction technique is discussed and dependence of thermal resistance on fin width, number of parallel fins and fin spacing is studied.
    Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2011 IEEE 11th Topical Meeting on; 02/2011
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    ABSTRACT: 1. Abstract Self-heating and substrate effects are discussed and qualitatively compared in the ultra-thin body ultra-thin BOX (UTB 2) devices without a ground plane. Ultra-thin body is aggravating thermal properties of the devices due to the interface effects. Ultra-thin BOX (10 nm) improves heat dissipation from the channel to the bulk silicon substrate but also results in strongly pronounced substrate effects. It is observed that output conductance degradation in the UTB 2 devices due to the substrate effects can be as strong as degradation due to the self-heating.
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    ABSTRACT: The frequency variation of the output conductance in ultra-thin body with ultra-thin BOX (UTBB) SOI MOSFETs without a ground plane is studied through measurements and two-dimensional simulations. Two effects causing the output conductance variation with frequency, namely self-heating and source-to-drain coupling through the substrate, are discussed and qualitatively compared. Notwithstanding the use of ultra-thin BOX, which allows for improved heat evacuation from the channel to the Si substrate underneath BOX, a self-heating-related transition clearly appears in the output conductance frequency response. Furthermore, the use of an ultrathin BOX results in an increase of the substrate-related output conductance variation in frequency. As a result, the change in output conductance of UTBB MOSFETs caused by the substrate effect appears to be comparable and even stronger than the change due to self-heating.
    Solid-state Electronics - SOLID STATE ELECTRON. 01/2011;
  • MRS Online Proceeding Library 01/2011; 809.
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    ABSTRACT: The self-gain of surface channel compressively strained SiGe pMOSFETs with HfSiOx/TiSiN gate stacks is investigated for a range of gate lengths down to 55 nm. There is 125% and 700% enhancement in the self-gain of SiGe pMOSFETs compared with the Si control at 100 nm and 55 nm lithographic gate lengths, respectively. This improvement in the self-gain of the SiGe devices is due to 80% hole mobility enhancement compared with the Si control and improved electrostatic integrity in the SiGe devices due to less boron diffusion into the channel. At 55 nm gate length, the SiGe pMOSFETs show 50% less drain induced barrier lowering compared with the Si control devices. Electrical measurements show that the SiGe devices have larger effective channel lengths. It is shown that the enhancement in the self-gain of the SiGe devices compared with the Si control increases as the gate length is reduced thereby making SiGe pMOSFETs with HfSiOx/TiSiN gate stacks an excellent candidate for analog/mixed-signal applications.
    Microelectronic Engineering 11/2010; 87(11):2196-2199. · 1.34 Impact Factor
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    ABSTRACT: Strained Si and strained SiGe layers can increase the speed of MOS devices through enhanced electron and hole mobilities compared with bulk Si. However, epitaxial growth of strained Si and SiGe layers induces surface roughness which impacts gate dielectric properties including leakage, breakdown and interface traps. Gate dielectric quality is conventionally studied at a macroscopic level on individual transistors or capacitors. To understand precisely the effect of roughness on the quality and reliability of dielectrics on high mobility substrate devices requires high spatial resolution characterisation techniques. Device processing modifies the dielectric/semiconductor interface compared with its initial form. Therefore nanoscale analysis on completed devices is necessary. In this work, we present new techniques to enable gate leakage analysis on a nanoscale in fully processed high mobility MOSFETs. This is achieved by careful selective removal of the gate from the dielectric followed by C-AFM measurements on the dielectric surface. Raman spectroscopy, AFM and SEM (EDX) confirmed complete layer removal. The techniques are applied to strained Si devices which have different surface morphologies and different macroscopic electrical data. Dielectric reliability is also assessed through device stressing.
    Microelectronics Reliability 09/2010; 50:1484-1487. · 1.21 Impact Factor
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    ABSTRACT: Experimental and modeling results are reported for high-performance strained-silicon heterojunction bipolar transistors (HBTs), comprising a tensile strained-Si emitter and a compressively strained Si<sub>0.7</sub>Ge<sub>0.3</sub> base on top of a relaxed Si<sub>0.85</sub>Ge<sub>0.15</sub> collector. By using a Si<sub>0.85</sub>Ge<sub>0.15</sub> virtual substrate strain platform, it is possible to utilize a greater difference in energy band gaps between the base and the emitter without strain relaxation of the base layer. This leads to much higher gain, which can be traded off against lower base resistance. There is an improvement in the current gain β of 27 × over a conventional silicon bipolar transistor and 11× over a conventional SiGe HBT, which were processed as reference devices. The gain improvement is largely attributed to the difference in energy band gap between the emitter and the base, but the conduction band offset between the base and the collector is also important for the collector current level.
    IEEE Transactions on Electron Devices 07/2010; · 2.36 Impact Factor
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    ABSTRACT: Measuring strain in long-channel MOSFETs on silicon-on-insulator (SOI) and strained-SOI platforms is demonstrated using ultraviolet (UV) Raman spectroscopy. Removal of the Raman inactive strain-inducing metallization layers is avoided by etching trenches under transistors without mask alignment in order to expose the channel region. The technique is shown to be repeatable and does not alter the initial strain state in the channel. The applicability of this technique to short-channel transistors is also discussed.
    IEEE Electron Device Letters 06/2010; · 3.02 Impact Factor
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    ABSTRACT: As gate dielectrics are scaled to a few atomic layers and the channel doping is increased to mitigate short channel effects, high vertical electric fields cause considerable mobility degradation through surface-roughness scattering in silicon MOSFETs. This high-field mobility degradation is known to influence the harmonic distortion through higher order derivatives of the drain current. Failure to take these higher order derivatives into account can cause significant error in the predictive evaluation of linearity (VIP3) in MOSFETs. Electrical measurements are used to extract the 2nd order mobility degradation factor (θ2) from strained silicon MOSFETs fabricated on silicon germanium strain relaxed buffers with 15%, 20% and 25% germanium. Linearity and high-field mobility degradation are shown to be independent of strain in spite of atomic force microscopy measurements showing that the amplitude of the root-mean-square surface roughness increases with the germanium content. It is also shown that θ2 is required for accurate modelling of linearity. The impact of oxide thickness on linearity is also investigated through θ2. In this paper, an analytical relationship between θ2 and the effective oxide thickness is developed and validated by electrical measurements on MOSFETs with different oxide thicknesses and θ2 values from the literature. Using the extracted θ2 values as inputs to analytical MOSFET models, a correlation between the oxide thickness and linearity is analyzed.
    Solid-State Electronics 06/2010; · 1.51 Impact Factor

Publication Stats

495 Citations
121.35 Total Impact Points


  • 2002–2013
    • Newcastle University
      • School of Electrical and Electronic Engineering
      Newcastle-on-Tyne, England, United Kingdom
  • 2009
    • University of Newcastle
      • Department of Computer Engineering
      Newcastle, New South Wales, Australia
  • 2004–2008
    • Imperial College London
      • Department of Electrical and Electronic Engineering
      London, ENG, United Kingdom