M.M. Chowdhury

Freescale Semiconductors, Inc, Austin, Texas, United States

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Publications (12)9.25 Total impact

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    ABSTRACT: In this paper we investigate state-of-the-art undoped channel FinFETs and FinDiodes with an emphasis on I/O and ESD applicability. Utilizing electrical characterization data, 3D TCAD, and a compact model, we demonstrate that FinFETs and FinDiodes exhibit a very appealing combination of high breakdown voltage and low Ioff for I/O and ESD protection circuit applications.
    Reliability Physics Symposium, 2008. IRPS 2008. IEEE International; 01/2008
  • Murshed M. Chowdhury, V.P. Trivedi, J.G. Fossum, Leo Mathew
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    ABSTRACT: A process/physics-based double-gate (DG) MOSFET model (UFDG), which includes a quantum-based carrier mobility model, is used to examine carrier transport in undoped ultrathin-silicon bodies/channels. The model predicts for {100}-surface devices, in accord with measurements, effective electron and hole mobilities that are dramatically higher than those in contemporary bulk-Si MOSFETs at the same integrated inversion-carrier density. Calibration of UFDG to undoped p- and n-channel DG FinFETs yields consistent results, showing very high mobilities in contemporary FinFETs, implying relatively smooth {110} fin-sidewall surfaces, and giving new insights on electron and hole mobilities in DG MOSFETs with {110} versus {100} surfaces. The calibrated model is used to simulate 17.5-nm DG FinFETs with midgap gates, predicting ballistic-like currents and, hence, suggesting that strained-Si channels are not needed for mobility enhancement in these nonclassical devices
    IEEE Transactions on Electron Devices 06/2007; · 2.36 Impact Factor
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    M.M. Chowdhury, J.G. Fossum
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    ABSTRACT: Calibration of a physics/process-based model for double-gate (DG) MOSFETs to contemporary nanoscale undoped n-channel DG FinFETs reveals that 1) significant densities of source/drain donor dopants readily diffuse to the ultrathin (fin) body/channel, even with relatively long fin extensions, degrading electron mobility at low/moderate levels of inversion-carrier density (N<sub>inv</sub>), 2) surface-roughness scattering of electrons is less severe at the {110} silicon-fin surfaces than anticipated, and 3) strong-inversion electron mobility is quite high (e.g., ≅290 cm<sup>2</sup>/V·s at N<sub>inv</sub>=10<sup>13</sup> cm<sup>-2</sup>), being about three times higher than that in contemporary bulk-Si MOSFETs.
    IEEE Electron Device Letters 07/2006; · 3.02 Impact Factor
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    ABSTRACT: In this paper we demonstrate for the first time a novel CMOS IT-FET (inverted T channel FET) architecture. We demonstrate well functional ITFET SRAM bit-cells. Vertical devices such as FinFET and planar ultra thin body devices have been shown to exhibit good short channel control and proposed for future device scaling. The ITFET is novel device architecture that takes advantage of both vertical and horizontal thin-body devices. A doped channel IT-FET process has been developed and is the focus of this paper. This technology can be scaled beyond 45nm technologies using undoped channels. An ITFET device comprises of an ultra thin body planar horizontal channels and vertical channels in a single device. The devices have multi-gate control around these channels to improve short channel control. A single device has multiple orientations and hence mobility enhancement of both (110) and (100) planes can be used optimally. The devices presented have 15nm planar horizontal thin body and 40nm vertical channels of 100nm height, 17Aring gate dielectric and 50nm gate length. These devices are especially useful in circuits that need ratioing such as in SRAM cells and a well functional SRAM cell is demonstrated
    Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
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    ABSTRACT: The ITFET is novel device architecture; it offers significant advantages over planar and FinFET technologies. The ITFET uses traditional CMOS processing technologies and can be rapidly inserted into existing SOI process flows. Doped channel ITFET devices have been demonstrated future work will include undoped channel ITFET devices. Simulated performances of the ITFET devices predict these devices can meet the 45nm and 32nm device performance. This transistor architecture offers device, process and application advantages
    Integrated Circuit Design and Technology, 2006. ICICDT '06. 2006 IEEE International Conference on; 01/2006
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    ABSTRACT: Physics-based compact modeling, as opposed to the conventional empirical approach, is emphasized for nanoscale nonclassical CMOS. UFDG, a physics-based compact model for generic double-gate MOSFETs with ultra-thin bodies, is overviewed, and its applications to double- and (multiple) independent-gate FinFET device and circuit design are demonstrated.
    Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on; 12/2005
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    ABSTRACT: MIGFET devices have multiple gates to independently control the channel region. This allows for new device architectures and applications. This paper deals with three novel aspects discussed the first time I) Multi-fin MIGFET device with two independent gates capable of high current drives has been fabricated and demonstrated as a RF Mixer II) For the first time a MOSFET with three independent gates has been fabricated. These devices can be used in single transistor memories III) MIGFET has been used to characterize temperature effects on double gate devices in single electrode and independent gate modes. The three aspects discussed in the paper will have significant impact on future applications of these devices. The MIGFET can be integrated with double gate devices enabling novel analog circuits to scale with multi-gated digital CMOS in future digital CMOS transceiver (Single Chip Radio). The third independent gate in the MIGFET-T device enables novel memory architectures. Temperature characterization reveals the double gate Vt can be shifted both by temperature and by the second gate bias. This data enables compact modeling of temperature effects on independent gate devices to evaluate circuits that take advantage of this characteristic of the MIGFET.
    VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
  • V. Trivedi, J.G. Fossum, M.M. Chowdhury
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    ABSTRACT: Using two-dimensional numerical device simulations, we show that optimally designed nanoscale FinFETs with undoped bodies require gate-source/drain (G-S/D) underlap that can be effectively achieved via large, doable straggle in the S-D fin-extension doping profile without causing S-D punch-through. The effective underlap significantly relaxes the fin-thickness requirement for control of short-channel effects (SCEs) via a bias-dependent effective channel length (L<sub>eff</sub>), which is long in weak inversion and approaches the gate length in strong inversion. Dependence of L<sub>eff</sub> on the S/D doping profile defines a design tradeoff regarding SCEs and S/D series resistance that can be optimized, depending on the fin width, via engineering of the doping profile in the S/D fin-extensions. The noted optimization is exemplified via a well-tempered FinFET design with an 18-nm gate length, showing further that designs with effective underlap yield minimal parasitic capacitance and reduce leakage components such as gate-induced drain leakage current.
    IEEE Transactions on Electron Devices 02/2005; · 2.36 Impact Factor
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    ABSTRACT: A process/physics-based compact model (UFDG) for nonclassical MOSFETs having ultra-thin Si bodies (UTB) is overviewed. The model, in essence, is a compact Poisson–Schrödinger solver, including accountings for short-channel effects, and is applicable to nanoscale fully depleted (FD) SOI MOSFETs as well as generic double-gate (DG) devices. The utility of UFDG in nonclassical CMOS device design, as well as circuit design, is stressed, and demonstrated by using it in Spice3 to design UTB MOSFETs and to project extremely scaled DG and FD/SOI CMOS performances. Also, calibration of UFDG to fabricated FinFETs yields new physical insights about these potentially viable nanoscale DG devices, and about model requirements for them.
    Solid-State Electronics 06/2004; 48(6):919-926. · 1.51 Impact Factor
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    ABSTRACT: An array of measured device data, a numerical device simulator, and a process/physics-based compact model are used to gain new and important physical insights on nanoscale FinFETs with undoped thin-fin bodies. The insights, which include unavoidable/needed gate underlap, bias-dependent effective channel length, and non-ohmic fin-extension voltage drops, reveal the significance of gate positioning on, and source/drain doping profile in, the thin fin, and imply novel compact modeling that will be needed for optimal design of nonclassical CMOS circuits.
    Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004
  • M. M. Chowdhury, V. P. Trivedi, J. G. Fossum, L. Mathew
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    ABSTRACT: In this paper we calibrate our process/physics-based DG MOSFET model (UFDG (Fossum, et. al., 2004)) to contemporary DG FinFETs, and examine carrier mobilities in the undoped UTBs. The calibrated model is also used to give interesting insights on carrier transport in nanoscale DG FinFETs that contradict ITRS projections
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Publication Stats

226 Citations
9.25 Total Impact Points


  • 2006
    • Freescale Semiconductors, Inc
      Austin, Texas, United States
  • 2005–2006
    • University of Florida
      • Department of Electrical and Computer Engineering
      Gainesville, Florida, United States