-
V. Narayanan, K. Maitra,
B.P. Linder,
V.K. Paruchuri,
E.P. Gusev,
P. Jamison,
M.M. Frank,
M.L. Steen,
D. La Tulipe,
J. Arnold,
R. Carruthers,
D.L. Lacey,
E. Cartier
[show abstract]
[hide abstract]
ABSTRACT: The performance of aggressively scaled (1.4nm<T<sub>inv</sub><2.1nm) self-aligned HfO<sub>2</sub>-based nMOSFETs with various metal gate electrodes (W, TaN, TiN, and TaSiN) is optimized. It is shown that high mobility values, competitive with oxynitride controls (SiON/poly-Si, T<sub>inv</sub>∼1.8-2.1nm), can be achieved. Detailed studies of the role of interface states, remote charges in the HfO<sub>2</sub> layer, interfacial layer regrowth, and nitrogen-induced charge lead to the conclusion that high-temperature-induced structural modifications near the SiO<sub>2</sub>/HfO<sub>2</sub> interface substantially improve the electron mobility.
IEEE Electron Device Letters 08/2006; · 2.85 Impact Factor
-
M.M. Frank,
V.K. Paruchuri,
V. Narayanan,
N. Bojarczuk,
B. Linder,
S. Zafar,
E.A. Cartier,
E.P. Gusev,
P.C. Jamison,
K.L. Lee, [......], K. Maitra,
X. Wang,
P.M. Kozlowski,
J.S. Newbury,
D.R. Medeiros,
P. Oldiges,
S. Guha,
R. Jammy,
M. Ieong,
G. Shahidi
[show abstract]
[hide abstract]
ABSTRACT: We demonstrate poly-Si/high-k gate stacks suitable for successful implementation in low power technologies. An optimized gate dielectric process was employed to suppress the large pFET threshold voltage shift commonly found with Hf-based gate dielectrics, reducing it to -0.2 V, while preserving pFET and nFET device performance.
VLSI Technology, 2005. (VLSI-TSA-Tech). 2005 IEEE VLSI-TSA International Symposium on; 05/2005
-
E.P. Gusev,
V. Narayanan,
S. Zafar,
C. Cabral Jr,
E. Carrier,
N. Bojarczuk,
A. Callegari,
R. Carruthers,
M. Chudzik,
C. D'Emic,
E. Duch,
P. Jamison,
P. Kozlowski,
D. LaTulipe, K. Maitra,
F.R. McFeely,
J. Newbury,
V. Paruchuri,
M. Steen
[show abstract]
[hide abstract]
ABSTRACT: A comparative analysis of charge trapping in advanced metal gate/high-k stacks with EOT below 1 nm (corresponding to CETs, or T<sub>inv</sub>, in the 1.2-1.5 nm range) has been carried out. We investigate the effects of: (i) gate electrode material (namely, various metals vs. fully silicided gates (FUSI) vs. conventional poly-Si gates); (ii) high-k dielectric material (HfO<sub>2</sub>, HfO<sub>2</sub>:N, HfSiO, HfSiON, ZrO<sub>2</sub>, Al<sub>2</sub>O<sub>3</sub>); (iii) high-k deposition technique (MOCVD vs. ALD); (iv) bottom interface; and (v) annealing effects, both postdeposition (PDA) and in a forming gas (FGA). Significant improvement of charge trapping in all Me-gate stacks has been consistently demonstrated. Based on this systematic analysis, we come to a conclusion that interaction(s) between the high-k layer and poly-Si plays a major role in charge trapping degradation.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
-
E.P. Gusev,
C. Cabral Jr,
B.P. Under,
Y.H. Kim, K. Maitra,
E. Carrier,
H. Nayfeh,
R. Amos,
G. Biery,
N. Bojarczuk, [......],
H. Ng,
P. Nguyen,
J. Newbury,
V. Paruchuri,
R. Rengarajan,
G. Shahidi,
A. Steegen,
M. Steen,
S. Zafar,
Y. Zhang
[show abstract]
[hide abstract]
ABSTRACT: The key result in this work is that FUSI/HfSi<sub>x</sub>O<sub>y</sub> gate stacks offer both significant gate leakage reduction (due to high-κ) and drive current improvement at T<sub>inv</sub> ∼ 2 nm (due to: (i) elimination of poly depletion effect, ∼ 0.5 nm, and (ii) the high mobility of HfSi<sub>x</sub>O<sub>y</sub>). We also demonstrate that threshold voltage for both PFETs and NFETs can be adjusted from midgap to the values of Vt(PFET)∼ -0.4 V and Vt(NFET) ∼ + 0.3 V by poly-Si predoping by implantation (Al or As) and FUSI alloying. Significantly improved charge trapping (V<sub>t</sub> stability) was found in the case of NiSi/ HfSi<sub>x</sub>O<sub>y</sub> compared to the same gate electrode with HfO<sub>2</sub> dielectric.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
