[Show abstract][Hide abstract] ABSTRACT: SRAM cell stability will be a primary concern for future technologies due to variability and decreasing power supply voltages. 6T-SRAM can be optimized for stability by choosing the cell layout, device threshold voltages, and the β ratio. 8T-SRAM, however, provides a much greater enhancement in stability by eliminating cell disturbs during a read access, thus facilitating continued technology scaling. We demonstrate the smallest 6T (0.124μm<sup>2</sup> half-cell) and full 8T (0.1998μm<sup>2</sup>) cells to date.
[Show abstract][Hide abstract] ABSTRACT: A 0.143 μm<sup>2</sup> 6T-SRAM cell has been fabricated using a planar SOI technology with mixed electron-beam and optical lithography. This is the smallest functional 6T-SRAM cell ever reported - consistent with cell areas beyond the 32 nm technology node. Enabling process features include a 25 nm SOI layer, shallow trench isolation (STI), 45 nm physical gates with ultra-narrow 15 nm spacers, novel extremely thin cobalt disilicide, 50 nm tungsten plug contacts, and damascene copper interconnects. Device threshold voltages (V<sub>T</sub>) and cell beta ratio (β) are optimized for cell stability at these aggressive ground rules. The 0.143 μm<sup>2</sup> 6T-SRAM cell exhibits a static noise margin (SNM) of 148 mV at V<sup>DD</sup>=1.0 V.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005