Day-Uei Li

National Chiao Tung University, Hsinchu, Taiwan, Taiwan

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Publications (9)3.06 Total impact

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    Day-Uei Li, Chia-Ming Tsai
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    ABSTRACT: A novel intrinsic collector-base capacitance (C<sub>CB</sub>) feedback network (ICBCFN) was incorporated into the conventional cascode and series-connected voltage balancing (SCVB) circuit configurations to implement 10-Gb/s modulator drivers. The drivers fabricated in 0.35-μm SiGe BiCMOS process could generate 9 V<sub>PP</sub> differential output swings with rise/fall time of less than 29 ps. Also, the ICBCFN was modified as an intrinsic drain-gate capacitance feedback network (IDGCFN) to implement drivers with differential output swing of 8 V<sub>PP</sub> in 0.18-μm CMOS process. The power consumption is as low as 0.6 W. The present work shows that the driving capability is greater than that of the currently reported silicon-based drivers.
    IEEE Journal of Solid-State Circuits 06/2006; · 3.06 Impact Factor
  • Day-Uei Li, Chia-Ming Tsai
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    ABSTRACT: A burst/continuous-mode laser driver for 10Gb/s Ethernet PONs is implemented in a 0.18mum CMOS process. With a dual-loop current-mode control circuit, the driver automatically compensates the extinction ratio of the laser output. Under burst-mode operation, the laser turn on/off time is <3ns
    Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International; 03/2006
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    ABSTRACT: A 1.25 Gbps burst-mode optical receiver for Ethernet passive optical networks is realized in a 0.35 μm SiGe BiCMOS process. With dual-TIA topology, the sensitivity and overload of the receiver can be optimized independently. The measured results show a dynamic range of -28.4 dBm to -1 dBm and settling time less than 50 ns.
    Radio Frequency integrated Circuits (RFIC) Symposium, 2005. Digest of Papers. 2005 IEEE; 07/2005
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    ABSTRACT: A novel intrinsic collector-base capacitance (C<sub>CB</sub>) feedback network (ICBCFN) is incorporated into the conventional cascode circuit configuration to implement a 10-Gb/s modulator driver in 0.35 μm SiGe BiCMOS technology. The driver integrated circuit (IC) could output 9 V<sub>PP</sub> differential or 4.5 V<sub>PP</sub> single-ended (S.E.) output swing with rise/fall time less than 29 ps while it consumes power as low as 0.8 W. The performance and simulation results compared with preceding works are also shown in this paper. The proposed driver consumes the lowest power and occupies the smallest die area, and its output swing spans wider than the commonly-reported silicon-based modulator drivers.
    Radio Frequency integrated Circuits (RFIC) Symposium, 2005. Digest of Papers. 2005 IEEE; 07/2005
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    ABSTRACT: This paper presents 10-Gb/s modulator drivers employing novel cascode configuration with double output swing. The cascode drivers in 0.35μm SiGe BiCMOS technology exhibit high output swing of 4.5 V<sub>pp</sub>. It is the highest value among reported silicon-based drivers.
    VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). 2005 IEEE VLSI-TSA International Symposium on; 05/2005
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    ABSTRACT: A burst-mode transmitter with automatic power control which is capable of waveform shaping, fast laser on/off switching, and driving over 60mA modulation current is presented in this paper. It is constructed by a driver which was fabricated in 0.25μm 1P5M CMOS process with a 2.5-Gb/s 1310nm-wavelength Fabry-Perot laser diode. Measurements show clear eye diagrams operating over 2.5-Gb/s data rate with 84/97ps rise/fall times. The turn on/off delay of modulation current is less than 6ns. And the laser turn on/off time is about 30/20ns which is applicable for EPON or even GPON applications.
    VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). 2005 IEEE VLSI-TSA International Symposium on; 05/2005
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    ABSTRACT: This paper describes the design of a 10Gb/s laser diode (LD) driver in a 0.35μm SiGe BiCMOS technology. The LD driver delivers a biased current up to 60 mA, and a modulation current ranges from 40 mA to 100 mA. High speed operation as well as high current driving capability are achieved by means of push-pull current switching scheme. In addition, negative Miller capacitor compensation technique is adopted to enhance the signal bandwidth. The output swing of the predriver is dynamically adjustable to compromise between operating speed and overshoot. Both the modulation and biased currents are derived from a bandgap reference source. The measured rise/fall time is 47ps, and timing jitter is 22.2ps<sub>p-p</sub>. The eye diagrams meet the specifications defined by SONET OC-192 and 10G Ethernet eye mask. Operating under 3.3V/7V supply, the total power consumption is 1.38W. Chip size is 1430 x 940 μm<sup>2</sup>.
    VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). 2005 IEEE VLSI-TSA International Symposium on; 05/2005
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    ABSTRACT: A laser driver capable of driving over 100 mA modulation current fabricated in 0.35μm SiGe BiCMOS process was presented in this work. Measurements on mounted chips show clear electrical eye diagrams over 14-Gb/s data rate with a typical (20% to 80%) 24 ps rise time, 26 ps (20% to 80%) fall time, and a jitter (RMS) less than 2 ps. Moreover, optical eye diagram is also demonstrated by connecting the driver with a commercial 10-Gb/s 1310-nm laser diode and it stays well within the 10-Gb/s Ethernet transmitter mask.
    Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on; 01/2005
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    ABSTRACT: A 3.5-Gb/s burst-mode laser driver with automatic power control (APC) fabricated in 0.25 μm 1P5M CMOS process is presented. With the proposed waveform shaping circuit, the driver could operate under a single 3.3 V power supply without sacrificing output headroom, and it could output 6 mA to 60 mA modulation current with negligible overshoot. Measurements on mounted chips show clear electrical eye diagrams operating over 3.5-Gb/s data rate with typical rise/fall times (20% to 80%) of 84/97 ps. Moreover, an optical eye diagram is also demonstrated by connecting the driver to a 1.25-Gb/s 1310 nm laser diode. The laser turn on/off time is about 30/20 ns, much less than the criterion (512 ns) that the IEEE 802.3ah standard has proposed.
    International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan; 01/2005