Publications (53)53.69 Total impact
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Article: Pseudo-potential Band Structure Calculation of InSb Ultra-thin Films and its application to assess the n-Metal-Oxide-Semiconductor Transistor Performance
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ABSTRACT: Band structure of InSb thin films with $<100>$ surface orientation is calculated using empirical pseudopotential method (EPM) to evaluate the performance of nanoscale devices using InSb substrate. Contrary to the predictions by simple effective mass approximation methods (EMA), our calculation reveals that $\Gamma$ valley is still the lowest lying conduction valley. Based on EPM calculations, we obtained the important electronic structure and transport parameters, such as effective mass and valley energy minimum, of InSb thin film as a function of film thickness. Our calculations reveal that the 'effective mass' of $\Gamma$ valley electrons increases with the scaling down of the film thickness. We also provide an assessment of nanoscale InSb thin film devices using Non-Equilibrium Green's Function under the effective mass framework in the ballistic regime.09/2011; -
Article: SPICE Behavioral Model of the Tunneling Field-Effect Transistor for Circuit Simulation
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ABSTRACT: The tunneling field-effect transistor (TFET) is an alternative device for deep-submicrometer CMOS with very good short channel and leakage characteristics. In this brief, a SPICE behavioral model that well captures the I- V characteristics and the parasitic capacitance of the n-channel TFET is proposed to facilitate efficient circuit design and simulation. The validity of the model is verified with technology computer-aided design (TCAD) simulation. The accuracy is within 10% and is of an order of magnitude faster than the TCAD.Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2010; · 1.41 Impact Factor -
Article: Selenium Segregation for Lowering the Contact Resistance in Ultrathin-Body MOSFETs With Fully Metallized Source/Drain
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ABSTRACT: We report the first integration of selenium (Se) segregation contact technology in ultrathin-body (UTB) n-MOSFET featuring Ni fully silicided source and drain. During the Ni silicidation process, the implanted Se segregated at the NiSi-n-Si interface, leading to significant reduction of Schottky barrier height and contact resistance. The UTB n-MOSFETs integrated with Se segregation (SeS) contact technology show significant external series resistance reduction and drive current performance enhancement. Drain-induced barrier lowering and gate leakage current density are not adversely affected by the SeS process.IEEE Electron Device Letters 11/2009; · 2.85 Impact Factor -
Article: Contact Resistance Reduction Technology Using Selenium Segregation for N-MOSFETs With Silicon–Carbon Source/Drain
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ABSTRACT: We report the integration of a novel selenium segregation (SeS) technology in the silicide contact of strained n-MOSFETs featuring silicon-carbon Si<sub>0.99</sub>C<sub>0.01</sub> source/drain (S/D) stressors. SeS at the NiSi:C/n-Si<sub>0.99</sub> C<sub>0.01</sub> interface leads to the achievement of low Schottky barrier height and reduced silicide contact resistance R <sub>CSD</sub>. At a fixed I <sub>OFF</sub> of 100 nA/ mum, the improved silicide contact technology employing SeS contributed to a 20% drive current I <sub>ON</sub> enhancement and 30% total series resistance R <sub>Total</sub> reduction over control strained devices. The R <sub>Total</sub> improvement is primarily due to the reduction of external series resistance R <sub>EXT</sub>, which is due to a reduced R <sub>CSD</sub> at the NiSi:C/n- Si<sub>0.99</sub>C<sub>0.01</sub> interface. Comparable DIBL, V <sub>Tsat</sub> and gate leakage density were observed for strained n-MOSFETs with or without the SeS. The impact of introducing Se in the embedded Si<sub>0.99</sub>C<sub>0.01</sub> S/D stressor on tensile stress level in the channel region of strained n-MOSFET was also investigated.IEEE Transactions on Electron Devices 06/2009; · 2.32 Impact Factor -
Article: A Variational Approach to the Two-Dimensional Nonlinear Poisson's Equation for the Modeling of Tunneling Transistors
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ABSTRACT: In this letter, we report a new approach to treat the 2-D nonlinear Poisson's equation in the context of MOS devices and discuss its application in the modeling of tunneling field-effect transistors (T-FET). It is revealed that the narrowing of tunneling barrier in T-FET has different mechanisms before and after inversion layer is formed. Closed-form equation is obtained to describe the barrier narrowing in the presence of inversion layer.IEEE Electron Device Letters 12/2008; · 2.85 Impact Factor -
Article: Novel Nickel Silicide Contact Technology Using Selenium Segregation for SOI N-FETs With Silicon–Carbon Source/Drain Stressors
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ABSTRACT: We explore a novel silicide contact technology for effective Schottky barrier height Phi<sub>Bn</sub> and contact resistance reduction, which is compatible with an advanced silicon-carbon (Si<sub>1-x</sub>C<sub>x</sub>) source/drain (S/D) stressor technology. The new silicide contact technology incorporates selenium (Se) that is coimplanted with S/D dopants into the silicon-carbon S/D prior to nickel silicidation, leading to the segregation of Se at the NiSi:C/n-Si<sub>0.99</sub> C<sub>0.01</sub> interface and the achievement of excellent ohmic contact characteristics. We demonstrate that the Se-coimplantation process contributes to a 23% drive current enhancement in a strained silicon-on-insulator n-MOSFET. The enhancement is attributed to the decrease of external series resistance which is primarily due to the reduction of silicide contact resistance.IEEE Electron Device Letters 09/2008; · 2.85 Impact Factor -
Article: Source and Drain Series Resistance Reduction for N-Channel Transistors Using Solid Antimony (Sb) Segregation (SSbS) During Silicidation
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ABSTRACT: We report the first integration of a novel solid antimony (Sb) segregation (SSbS) process in a transistor fabrication flow. A thin solid Sb layer, which acts as a large source of n-type dopants, was deposited beneath a metallic nickel layer prior to source-drain silicidation. Following nickel silicidation, a very high concentration of Sb was incorporated at the NiSi/Si interface. The SSbS process is demonstrated to reduce the effective Schottky barrier (SB) height and parasitic series resistance in an n-channel field-effect transistor, leading to enhanced drive current performance without degradation in the OFF -state leakage current. Performance enhancement is also maintained when the supply voltage is reduced from 1.3 to 0.8 V.IEEE Electron Device Letters 08/2008; · 2.85 Impact Factor -
Article: Cointegration of In Situ Doped Silicon–Carbon Source and Silicon–Carbon I-Region in P-Channel Silicon Nanowire Impact-Ionization Transistor
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ABSTRACT: The p-channel impact-ionization nanowire multiple- gate field-effect transistors (I-MuGFETs or I-FinFETs), which have a multiple-gate/nanowire-channel architecture, were demonstrated. The superior gate-to-channel coupling reduces the breakdown voltage V<sub>BD</sub> for enhanced device performance. For the first time, an in situ doped source was incorporated with the impact-ionization MOS transistor. The in situ phosphorus-doped Si source with improved dopant activation and very abrupt junction profile reduces V<sub>BD</sub> and enhances the on-state current I<sub>on</sub>. An additional improvement was also achieved by incorporating a strained Si<sub>1-y</sub>C<sub>y</sub> impact-ionization region (I-region) and an in situ doped Si<sub>1-y</sub>C<sub>y</sub> source, leading to reduction in Vbd and enhancement in I<sub>on</sub>. This is due to strain-induced reduction of the impact-ionization threshold energy E<sub>th</sub>. Furthermore, an excellent subthreshold swing of below 3 mV/decade at room temperature was achieved for all devices.IEEE Electron Device Letters 08/2008; · 2.85 Impact Factor -
Conference Proceeding: Performance enhancement schemes featuring lattice mismatched S/D stressors concurrently realized on CMOS platform: e-SiGeSn S/D for pFETs by Sn<sup>+</sup> implant and SiC S/D for nFETs by C<sup>+</sup> implant
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ABSTRACT: We report, for the first time, a simple and cost effective co-integration of strained p and n-FETs using tin (Sn) and mono-carbon (C) implant in Source/Drain (S/D) of p- and n-FETs, respectively, to induce beneficial strain. For the first time, a single laser anneal step was employed to substitutionally incorporate the Sn and C atoms simultaneously into lattice sites. 7 at.% substitutional Sn concentration (the equivalent of adding 35% Ge to SiGe S/D stressors) was achieved in the Si<sub>0.7</sub>Ge<sub>0.3</sub>S/D of Si channel p-FET. A significant enhancement of up to 150% in hole mobility and 71% in drive current for a 50 nm gate length device was observed. Mono C implanted S/D n-FETs show 19% current drive increase. With the simultaneous integration of Ni based FUSI gate, we provide a highly useful extension to future S/D technology for further I<sub>D,sat</sub> and mobility improvement.VLSI Technology, 2008 Symposium on; 07/2008 -
Conference Proceeding: Selenium Co-implantation and segregation as a new contact technology for nanoscale SOI N-FETs featuring NiSi:C formed on silicon-carbon (Si:C) source/drain stressors
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ABSTRACT: We report a novel contact technology comprising Selenium (Se) co-implantation and segregation to reduce Schottky barrier height Phi<sub>Bn</sub> and contact resistance for n-FETs. Introducing Se at the silicide-semiconductor interface pins the Fermi level near the conduction band, and achieves a record low Phi<sub>Bn</sub> of 0.1 eV on Si:C S/D stressors. Comparable sheet resistance and junction leakage are observed with and without Se segregation. When integrated in nanoscale SOI n-FETs with Ni-silicided Si:C S/D, the new Se-segregation contact technology achieves 36% reduction in total series resistance and 32% I<sub>ON</sub> enhancement. Linear transconductance G<sub>MLin</sub> also shows large enhancement in the sample with Se-segregated contacts.VLSI Technology, 2008 Symposium on; 07/2008 -
Article: Silicon–Carbon Stressors With High Substitutional Carbon Concentration and In Situ Doping Formed in Source/Drain Extensions of n-Channel Transistors
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ABSTRACT: We report the first demonstration of n-channel field-effect transistors (N-FETs) with in situ phosphorus-doped silicon-carbon (SiCP) stressors incorporated in the source/drain extension (SDE) regions. A novel process which formed recessed SDE regions followed by selective epitaxy of SiCP was adopted. High in situ doping contributes to low series resistance to channel resistance ratio and is important for reaping the benefits of strain. Substitutional carbon concentration was varied, showing enhanced drive current with increased for comparable off-state leakage, series resistance, and control of short-channel effects. A record high carbon substitutional concentration of 2.1% was achieved. Use of heavily doped silicon-carbon stressor with large lattice mismatch with respect to Si and placed in close proximity to the channel region in the SDE regions is expected to be important for strain engineering in nanoscale N-FETs.IEEE Electron Device Letters 06/2008; · 2.85 Impact Factor -
Conference Proceeding: A New Salicidation Process with Solid Antimony (Sb) Segregation (SSbS) for Achieving Sub-0.1 eV Effective Schottky Barrier Height and Parasitic Series Resistance Reduction in N-Channel Transistors
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ABSTRACT: We report a new CMOS-compatible salicidation process to achieve sub-0.1 eV effective Schottky barrier (SB) height for NiSi/n-Si, one of the lowest values reported-to-date, and its device integration for contact resistance reduction in n-FETs. A thin solid Antimony (Sb) layer is inserted beneath Ni prior to S/D silicidation, acting as a large source of n-type dopants. After silicidation, a very high concentration of Sb is incorporated at the NiSi/Si interface. This solid Sb segregation (SSbS) process reduces the effective SB height and parasitic series resistance. The SSbS process leads to enhanced n-FET performance without degradation in off-state leakage.VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on; 05/2008 -
Conference Proceeding: Realization of Silicon-Germanium-Tin (SiGeSn) Source/Drain Stressors by Sn implant and Solid Phase Epitaxy for strain engineering in SiGe channel P-MOSFETs
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ABSTRACT: We report the first demonstration of silicon-germanium-tin (SiGeSn) source and drain (S/D) stressors formed by Sn implant and solid-phase epitaxy (SPE). SPE was developed to achieve high levels of Sn substitutionality in SiGe S/D, to induce compressive strain in the channel. No recess etch or epi deposition steps were required, leading to minimal incremental process cost. SiGeSn S/D can be easily integrated in a standard CMOS process. Sub-50 nm p- FETs were fabricated. With a substitutional Sn concentration of 6.6% in SiGe S/D, having an equivalent lattice constant to that of Si<sub>0.4</sub>Ge<sub>0.6</sub>, enhancement of I<sub>Dsat</sub> and hole mobility (mu<sub>hole</sub>) are 48% and 88% respectively, over p-FETs without Sn implant. With the demonstration of SiGeSn S/D stressors, we provide a technology extension to SiGe S/D technology for further p-FET enhancement.VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on; 05/2008 -
Conference Proceeding: P-Channel I-MOS Transistor featuring Silicon Nano-Wire with Multiple-Gates, Strained Si1-yCy I-region, in situ doped Si1-yCy Source, and Sub-5 mV/decade Subthreshold Swing
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ABSTRACT: We realized Impact Ionization Nanowire Multiple-gate Field- Effect Transistors (I-MuGFETs or I-FinFETs) having a multiple- gate/nanowire-channel architecture to exploit the superior gate-to- channel coupling for reduced breakdown voltage VBD and enhanced device performance. The first p-channel Impact Ionization MOS transistor (I-MOS) having in situ doped source was also demonstrated. An in situ phosphorus-doped Si source with improved dopant activation and very abrupt junction profile reduces V<sub>BD</sub> and enhances the on-state current I<sub>on</sub>. A further improvement was also made by incorporating strained Si<sub>1-y</sub>C<sub>y</sub> impact-ionization region (I-region) and in situ doped Si<sub>1-y</sub>C<sub>y</sub> source, leading to further reduction in VBD and enhancement in I<sub>on</sub>. This is due to strain- induced reduction of the impact-ionization threshold energy E<sub>th</sub>. In addition, excellent subthreshold swing of below 5 mV/decade at room temperature was achieved for all devices.VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on; 05/2008 -
Article: A Double-Spacer I-MOS Transistor With Shallow Source Junction and Lightly Doped Drain for Reduced Operating Voltage and Enhanced Device Performance
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ABSTRACT: In this letter, a double-spacer (DS) design is utilized for the formation of shallow source and lightly doped drain to further optimize the impact-ionization MOS (I-MOS) transistor structure. The breakdown voltage V<sub>BD</sub> needed for avalanche breakdown is lowered due to the shallow source extension. With the formation of the lightly doped drain extension, the impact of drain bias on breakdown voltage, and hence, the threshold voltage V<sub>T</sub> is also reduced. The DS I-MOS is fabricated and characterized. Detailed analysis and physical explanation of the impact of drain/gate bias on the device characteristics are provided. Compared to the conventional I-MOS transistor, the shallow source extension reduces the breakdown voltage [drain-induced breakdown voltage lowering (DIBVL)] by 0.3-0.6 V, and the lightly doped drain extension reduces the DIBVL up to 0.17 V/V. In addition, excellent subthreshold swing and good device performance are achieved.IEEE Electron Device Letters 03/2008; · 2.85 Impact Factor -
Article: Strained Silicon–Germanium-On-Insulator n-MOSFET With Embedded Silicon Source-and-Drain Stressors
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ABSTRACT: In this letter, a strained silicon-germanium (SiGe) n-channel field-effect transistor (n-FET) featuring embedded silicon (Si) source-and-drain (S/D) stressors is demonstrated. A novel Ge-condensation technique was employed to form Si<sub>0.75</sub>Ge<sub>0.25</sub>-on-insulator (SGOI) substrates with excellent surface quality. Transistors with gate length L <sub>G</sub> down to 60 nm were fabricated on the SGOI substrates. The strained n-FETs incorporated Si S/D regions, which are lattice-mismatched with respect to the Si<sub>0.75</sub>Ge<sub>0.25</sub> channel, to induce uniaxial tensile strain in the Si<sub>0.75</sub>Ge<sub>0.25</sub> channel for electron mobility enhancement. This leads to a 36% rise in linear drain-current and a 21% rise in saturation drive current over control SiGe channel devices at a fixed off-state current. Increasing the recess depth in S/D regions prior to the selective epitaxial growth of Si increases the channel stress, thus, a higher saturation drive-current enhancement can be achieved.IEEE Electron Device Letters 02/2008; · 2.85 Impact Factor -
Article: Compact HSPICE model for IMOS device
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ABSTRACT: A compact HSPICE model has been developed for the newly proposed impact-ionisation MOS (IMOS) device for circuit simulation. Table lookup dependent sources and passive components have been employed to model the IMOS device. The approach shows good accuracy compared to time-consuming and non-scalable TCAD simulation of IMOS-based circuits.Electronics Letters 02/2008; · 0.96 Impact Factor -
Conference Proceeding: Silicon nano-wire impact ionization transistors with multiple-gates for enhanced gate control and performance
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ABSTRACT: Silicon nano-wire impact ionization multiple-gate field-effect transistor (i-mugfet or I-FinFET) with excellent subthreshold swing of less than 5 mV/decade at room temperature were demonstrated. Both n- and p- channel I-FinFET devices were realized. The multiple-gate structure enhances the gate-to-channel coupling effect and the impact-ionization rate in the fin or nanowire channel, thereby reducing the breakdown voltage and giving excellent device performance.Semiconductor Device Research Symposium, 2007 International; 01/2008 -
Conference Proceeding: Enhanced performance in strained n-FET with double-recessed Si:C source/drain and lattice-mismatched SiGe strain-transfer structure (STS)
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ABSTRACT: We report on further performance optimization in a novel n-channel transistor (n-FET) with beneath-the-channel strain-transfer structure (STS) and embedded silicon-carbon source/drain (Si:C S/D) stressors. The incorporation of SiGe STS couples additional strain from the S/D stressors to the overlying Si channel, leading to enhanced strain effects in the channel region. In addition, a two-step recess-etch was used to bring the double-recessed S/D stressors in closer proximity, increasing their lattice interactions with the channel and the STS, thereby significantly increasing the saturation drive current I<sub>on</sub>middot enhancement over control devices.Semiconductor Device Research Symposium, 2007 International; 01/2008 -
Conference Proceeding: Silicon-Germanium-Tin (SiGeSn) Source and Drain Stressors formed by Sn Implant and Laser Annealing for Strained Silicon-Germanium Channel P-MOSFETs
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ABSTRACT: We report a new silicon-germanium-tin (SiGeSn) source and drain stressor with large lattice-mismatch with respect to Si or SiGe for channel strain engineering, and its integration in a SiGe-channel p-FET for performance enhancement. A novel CMOS-compatible process was developed to incorporate Sn in SiGe S/D with high levels of Sn-substitutionality: Sn implant into Si<sub>0.75</sub>Ge<sub>0.25</sub> source and drain (S/D) regions, followed by either excimer laser annealing (LA) or solid phase epitaxy (SPE) to restore S/D crystallinity. Sub-50 nm p-FETs were fabricated. With a substitutional Sn concentration of 8% in SiGe S/D regions, equivalent to forming Si<sub>0.4</sub>Ge<sub>0.6</sub> in the S/D region, enhancement of I<sub>Dsat</sub> and hole mobility are 82% and 135%, respectively, over control p- FETs without Sn incorporation. With the first demonstration of SiGeSn S/D stressors, we provide a technology extension to SiGe S/D technology for further p-FFT enhancement.Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
Top co-authors
Top Journals
Institutions
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1992–2010
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National University of Singapore
- Department of Electrical & Computer Engineering
Singapore, Singapore
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2008
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University of Phoenix
Phoenix, AZ, USA
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