G.S. Samudra

Institute of Microelectronics, Tumasik, Singapore

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Publications (233)294.59 Total impact

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    ABSTRACT: Effective minority carrier lifetime reduction at low injection levels is observed on 125 mm undiffused lifetime samples whose surfaces are under inversion due to field-effect passivation. With numerical analysis, we show that edge recombination is insufficient to account for this phenomenon on these samples. Between surface damage and asymmetric bulk lifetimes mechanisms that can account for the reduction, surface damage is confirmed to be more plausible. We demonstrate that the measured effective lifetime curves can be well reproduced assuming surface damage, a 700 nm thin layer with much lower bulk lifetimes, with numerical simulation.
    the 40th IEEE Photovoltaic Specialist Conference, Denver, CO, USA; 06/2014
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    ABSTRACT: Multidimensional numerical simulation of boron diffusion is of great relevance for the improvement of industrial n-type crystalline silicon wafer solar cells. However, surface passivation of boron diffused area is typically studied in one dimension on planar lifetime samples. This approach neglects the effects of the solar cell pyramidal texture on the boron doping process and resulting doping profile. In this work, we present a theoretical study using a two-dimensional surface morphology for pyramidally textured samples. The boron diffusivity and segregation coefficient between oxide and silicon in simulation are determined by reproducing measured one-dimensional boron depth profiles prepared using different boron diffusion recipes on planar samples. The established parameters are subsequently used to simulate the boron diffusion process on textured samples. The simulated junction depth is found to agree quantitatively well with electron beam induced current measurements. Finally, chemical passivation on planar and textured samples is compared in device simulation. Particularly, a two-dimensional approach is adopted for textured samples to evaluate chemical passivation. The intrinsic emitter saturation current density, which is only related to Auger and radiative recombination, is also simulated for both planar and textured samples. The differences between planar and textured samples are discussed.
    Journal of Applied Physics. 01/2014; 116(18):184103.
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    ABSTRACT: During off-state, the influence of surface-trapped electron charges induced by high-field stress near the gate electrode of AlGaN/GaN power high-electron mobility transistor devices causes a reduction in two-dimensional electron gas (2DEG) carrier density at the heterointerface. In a pulse turn-on operation, the weakened 2DEG channel results in a higher on-state conduction resistance during the transient, known as the current collapse phenomenon. The phenomenon increases the switching loss by a higher on-state resistance and prolonged turn-on transition time, thus limits the device operating frequency range. In this paper, such a phenomenon is modeled, analyzed by Sentaurus TCAD simulation, and verified by the laboratory measurement data, with the emphasis on the influence of field plates toward the current collapse. The spatial distributions of trapped electrons and excess free electrons along the AlGaN surface are modeled and analyzed to arrive at the quantitative relationships among the trapped electron density, on-resistance increase, and the electric field distribution which provide a reliable criterion for current collapse reduction. It was found that, with a proper field plate design, it is possible to achieve an improvement on transient on-state resistance and the current recovery time.
    IEEE Transactions on Power Electronics 01/2014; 29(5):2164-2173. · 5.73 Impact Factor
  • H. Huang, Y.C. Liang, G.S. Samudra, C.L.L. Ngo
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    ABSTRACT: In this letter, partially recessed gate structures in conjunction with negative trap charges by ${rm F}^{-}$ plasma treatments both at AlGaN barrier and on gate dielectric surface are employed to realize the normally-OFF operation for AlGaN/GaN Metal-Insulator-Semiconductor High Electron Mobility Transistors in Au-free scheme. A partial gate recessed trench is designed to effectively reduce the 2-D electron gas (2DEG) density and achieve positive threshold voltage $({rm V}_{{rm th}})$ without severe degradation in 2-DEG channel mobility. Furthermore, the fixed trap charges are innovatively placed at the gate AlGaN and ${rm Si}_{{rm 3}}{rm N}_{{rm 4}}$ layers by a two-stage ${rm F}^{{-}}$ plasma treatment to further increase the ${rm V}_{{rm th}}$ , without mobility degradation. A high ${rm V}_{{rm th}}$ of 1.9 V and a drain current ${sim}{rm 200}~{rm mA}/{rm mm}$ are achieved in the fabricated device, which also has a lower leakage current and the higher breakdown voltage of 580 V.
    IEEE Electron Device Letters 01/2014; 35(5):569-571. · 2.79 Impact Factor
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    ABSTRACT: This paper reports extensive modelling and analysis of the temperature dependence on the device characteristics of the AlGaN/GaN high electron mobility transistors (HEMTs). A physics-based model is proposed in this study in order to correctly predict the gate flat-band Schottky barrier height, energy band Fermi-level (EC-EF) at the AlGaN/GaN interface, two-dimensional electron gas sheet density, gate threshold and (ID-VG) at sub-threshold voltages, and drain current-voltage (ID-VD) characteristics under various high-temperature conditions. The analytical results are then verified by comparing with the laboratory measurement as well as the numerical results obtained from the Sentaurus TCAD simulation. The proposed model is found to be useful for power electronic device designers on the prediction of the AlGaN/GaN HEMT device performance under high-temperature operation.
    Semiconductor Science and Technology 12/2013; 28(12):5010-. · 1.92 Impact Factor
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    ABSTRACT: The slow recovery in pulsed drain current in AlGaN/GaN power HEMTs caused by high voltage stress during off-state becomes an important research topic in power electronic switching applications. To further investigate this phenomenon, the influence of gate drive towards the drain current recovery is investigated in this paper. The gate drive current can influence the de-trapping process along the AlGaN device surface, which then in turn affecting the 2DEG conductivity for the on-state current recovery. The analysis is made through the physical model and 2D T-CAD Sentaurus simulations, and verified by the experimental measurement. The proposed work is able to assist engineers in gate drive design for AlGaN/GaN power HEMT devices for fast pulsed current recovery in high-frequency switching.
    Power Electronics and Drive Systems (PEDS), 2013 IEEE 10th International Conference on; 01/2013
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    ABSTRACT: This paper reports the studies of the temperature dependence on the current collapse behaviours of AlGaN/GaN high electron mobility transistors (HEMTs). A physical-based model is proposed to analyse the trapping and de-trapping process along the surface with the effect of temperature included for the first time. The temperature-dependent gate leakage current is treated as the source for electron trapping and it can be predicted by the proposed model quantitatively. Then the relationship of the capture cross section of the surface trap on the electric field is investigated with respect to temperature variations. By applying the Poole-Frenkel emission mechanism, the dynamics of the trapped electrons at different temperatures are described in this model. The analytical results on current recovery time-constant are then verified by comparing with the laboratory measurement as well as the numerical results obtained from Sentaurus TCAD simulations.
    Wide Bandgap Power Devices and Applications (WiPDA), 2013 IEEE Workshop on; 01/2013
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    ABSTRACT: The AlGaN/GaN high electron mobility transistor (HEMT) has drawn great interest in high power and high frequency applications owing to its outstanding material advantages, such as large critical electric field, high electron saturation velocity and the ability to form the high-density two dimensional electron gas (2DEG) conduction channel at the hetero interface. In this paper, a topical review on the device features is made, namely on its polarisation effects that lead to 2DEG formation at the AlGaN/GaN heterojunction, the surface field plate influence and the trap charges induced current collapse phenomenon during pulse operations. These effects are very important in understanding the AlGaN/GaN power HEMT devices.
    Next-Generation Electronics (ISNE), 2013 IEEE International Symposium on; 01/2013
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    ABSTRACT: Normally-off operation is strongly desired for safety and efficient power switching in order to make the HEMT devices compatible with the currently used Si based IGBT and MOSFET devices. Combination of partially gate recess etching and gate insulator interface or floating gate charges in MIS structures is proposed and demonstrated for the first time to realize the normally-off mode. Partially gate trench can effectively reduce 2DEG density and shift threshold voltage (Vth) to positive without severely degrading in 2DEG channel conductance, while gate insulator interface or floating gate charges can further increase Vth at a relatively low charge density and thus maintain normally-off mode at a much longer time. Sentaurus TCAD is used to systematically simulate and predict the characteristics of the proposed structures. A positive Vth of larger than 3 V is demonstrated by employment of gate recess with 5~10 nm barrier leftover in combination of gate dielectric charging with a low sheet density of ~1012 cm-2. The proposed structures are very promising in future power switching applications due to the large positive Vth and the low gate leakage current density by adjusting the gate insulator thickness.
    Power Electronics and Drive Systems (PEDS), 2013 IEEE 10th International Conference on; 01/2013
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    ABSTRACT: This paper reports analytical modelling and analysis of the temperature dependence on the device characteristics of the AlGaN/GaN high electron mobility transistors (HEMTs). A physics-based model is proposed in this study in order to correctly predict the gate Schottky barrier height (ΦB), Fermi-level from conduction band energy (EC-EF), two-dimensional electron gas (2DEG) sheet density, gate threshold (Vth) and sub-threshold voltages (ID-VG), and drain current-voltage (ID-VD) characteristics under various high temperature (300K~500K) conditions. The analytical results are then verified by comparing with the laboratory measurement as well as the numerical results obtained from the Sentaurus TCAD simulation. The proposed model is found to be useful for power electronic device designers on the prediction of the AlGaN/GaN HEMT device performance under high temperature operation without the use of heavy numerical solving process that requires complicated customized computer coding.
    ECCE Asia Downunder (ECCE Asia), 2013 IEEE; 01/2013
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    ABSTRACT: We present a computational study of the device performance of graphene nanoribbon tunneling field-effect transistors (TFETs) with a heterogeneous channel. By varying the length and the energy bandgap $(E_{G})$ of the heterogeneous region, the on- and off-state currents ( $I_{\rm ON}$ and $I_{\rm OFF}$ ) can be effectively optimized independently. Both semiconducting and semimetallic heterogeneous regions are studied to understand the effects of $E_{G}$ engineering on device behaviors. In addition, the effect of gate coverage (GC) over the heterogeneous region is also investigated. We found that device performance is greatly affected by the positioning of the gate to modify the region where band-to-band tunneling occurs. For a given $I_{\rm ON}/I_{\rm OFF}$ of eight orders, our results show that, for the semiconducting heterojunction, a higher $I_{\rm ON}$ can be obtained by having the gate partially covering the heterogeneous region. This is due to a combination of a short tunneling length and resonant states, which leads to an increase in carrier concentration for the tunneling mechanism. On the other hand, for the semimetallic case, a similar $I_{\rm ON}/I_{\rm OFF}$ is only attainable when the heterogeneous region is not covered by the gate. A large $I_{ \rm OFF}$ is observed for even small GC due to the valence electrons from the source traveling to the conduction bands of the semimetallic region, enhancing the carrier transport toward the drain. Our study highlights the device design consideration required when optimizing the device performance of heterojunction TFETs.
    IEEE Transactions on Electron Devices 01/2012; 59(5):1454-1461. · 2.06 Impact Factor
  • Shao-Ming Koh, Ganesh S. Samudra, Yee-Chia Yeo
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    ABSTRACT: In this work, strained n-channel FinFETs (nFinFETs) with silicon–carbon (Si:C) source/drain (S/D) stressors featuring NiSi:C contacts with segregated sulfur at the NiSi:C/Si:C interface are investigated in detail. The physical mechanism for the reduction in an effective Schottky barrier for electrons $\Phi_{B}^{n}$ due to presilicide sulfur ion implant and segregation is examined. The presence of sulfur near the NiSi:C/Si:C interface and its behavior as charged donor-like trap states was used to explain the enhancement of electron tunneling across the contact and the reduction in $\Phi_{B}^{n}$ down to 110 meV. New analysis using numerical simulation is presented. The results indicate that the presence of charged states near the interface plays a role in achieving low $\Phi_{B}^{n}$. When the S-segregated NiSi:C contact was integrated in strained nFinFETs with Si:C S/D stressors, external series resistance is reduced, and the drive current is improved. The dependence of the drive current on fin width and gate length is also studied.
    IEEE Transactions on Electron Devices 01/2012; 59(4):1046-1055. · 2.06 Impact Factor
  • Huolin Huang, Y.C. Liang, G.S. Samudra
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    ABSTRACT: In this paper, the influences of Al mole fraction and AlGaN layer strain relaxation on the bound polarization charges and the 2DEG concentration are investigated by theoretical calculation. The calculated sheet polarization charge data is used to preset Sentaurus TCAD to simulate the performance characteristics of the GaN HEMT device. The proposed method is proven to be a simple, equally accurate and effective approach in the simulations. For simplicity and time-saving, the theory-based hybrid method can be employed extensively in the simulations of GaN heterostructures power devices.
    Electron Devices and Solid State Circuit (EDSSC), 2012 IEEE International Conference on; 01/2012
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    ABSTRACT: Tellurium (Te) implantation was introduced to tune the effective electron Schottky barrier height (SBH) Φ<sub>B</sub><sup>n</sup> of platinum-based silicide (PtSi) contacts formed on n-type silicon-carbon (Si:C). Te introduced by ion implantation prior to Pt deposition segregated at the PtSi:C/Si:C interface during PtSi:C formation. The presence of Te at the PtSi:C/Si:C interface leads to a low Φ<sub>B</sub><sup>n</sup> of 120 meV for PtSi:C contacts. The integration of Te-segregated PtSi:C contacts on strained n-channel fin field-effect transistors (FinFETs) with Si:C source/drain (S/D) stressors achieves the lowering of the parasitic series resistance R <sub>SD</sub> by ~62% and increases the saturation drive current by ~22%. The Te-segregated contact-resistance reduction technology does not degrade the short-channel effects and positive-bias temperature instability characteristics of n-FinFETs with Si:C S/D. As PtSi has a low SBH for holes and is a suitable contact for p-FinFETs, this new contact-resistance reduction technology has potential to be introduced as a single-metal-silicide dual-barrier-height solution for future complementary metal-oxide-semiconductor FinFET technology.
    IEEE Transactions on Electron Devices 12/2011; · 2.06 Impact Factor
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    ABSTRACT: Band structure of InSb thin films with $<100>$ surface orientation is calculated using empirical pseudopotential method (EPM) to evaluate the performance of nanoscale devices using InSb substrate. Contrary to the predictions by simple effective mass approximation methods (EMA), our calculation reveals that $\Gamma$ valley is still the lowest lying conduction valley. Based on EPM calculations, we obtained the important electronic structure and transport parameters, such as effective mass and valley energy minimum, of InSb thin film as a function of film thickness. Our calculations reveal that the 'effective mass' of $\Gamma$ valley electrons increases with the scaling down of the film thickness. We also provide an assessment of nanoscale InSb thin film devices using Non-Equilibrium Green's Function under the effective mass framework in the ballistic regime.
    Semiconductor Science and Technology 09/2011; 23(2). · 1.92 Impact Factor
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    ABSTRACT: We report the demonstration of a new contact resistance reduction technology for n<sup>+</sup> Si S/D using Tellurium (Te) implant and segregation, achieving a low electron SBH of 0.11 eV. The Te implant reduced contact resistance in n-FinFETs by 40 %. When integrated in a process flow where Te is also introduced into the gate, improvement in gate electrostatic control is observed, leading to an improvement in ballistic efficiency. At I<sub>Off</sub> of 100 nA/μm, Te implant increases I<sub>On</sub> by 22 % as compared with control FinFETs without Te implant.
    VLSI Technology (VLSIT), 2011 Symposium on; 07/2011
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    ABSTRACT: The effect of 2-D electrostatic environment on the device performance of ultimately thin-body tunneling field-effect transistors (UTB-TFETs) using graphene nanoribbons (GNRs) is investigated by varying the gate-oxide thickness and insulating material with different dielectric constants (k ). Compared to Si TFETs with different body thicknesses, the atomic-layer-thick structure enhances the lateral fringing fields at the source-channel interface, resulting in a lower on-state current in GNR TFETs with high-k oxide as compared to the low-k variant of the same thickness. Low- k spacers are therefore essential to counter this effect and reap the benefits of high-k dielectrics in improving the device performance of UTB-TFETs.
    IEEE Electron Device Letters 05/2011; · 2.79 Impact Factor
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    ABSTRACT: We report a novel chemical vapor deposition (CVD) process for epitaxial growth of Ge film on GaAs substrate. The resultant layer exhibits device level quality, as shown by high-resolution transmission electron microscopy (HRTEM), Raman spectroscopy, high-resolution X-ray diffraction (HRXRD). In addition, atomic force microscopy (AFM) scanning indicates low RMS surface roughness of 5 Å. Secondary ion mass spectrometry (SIMS) reveals negligible out-diffusion of Ga and As into the Ge epilayer. By employing silane passivation, Ge p-MOSFET with TaN/HfO 2 gate stack was fabricated on Ge/GaAs heterostructure for the first time, showing excellent output and pinch-off characteristics. A GaAs channel n-MOSFET was also fabricated, using similar SiH 4 treatment during gate stack formation. These results reveal a potential solution to integrate Ge p-channel and GaAs n-channel MOSFET for advanced CMOS applications.
    MRS Online Proceeding Library 01/2011; 1068.
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    ABSTRACT: We investigated the device performance of graphene nanoribbon tunneling field-effect transistors with heterogeneous channel as a function of the contact doping concentrations. The simulations were carried out based on the non-equilibrium Green’s function, coupled with a Dirac Hamiltonian model, and the roles of symmetric and asymmetric contact doping concentrations on the device performance were identified. It was observed that the device performances such as OFF-state currents (IOFF), ON-state currents (ION) and subthreshold slopes (SSs) were greatly influenced by the source doping concentrations, while variations in drain doping concentrations changed mainly the IOFF. By applying proper asymmetric source and drain doping concentrations, low SS and large ION/IOFF ratio can be achieved, indicating that it is an alternative route to effectively enhance the device performance.
    Solid-State Electronics 01/2011; 77:1-2. · 1.48 Impact Factor
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    ABSTRACT: We report a new technique of achieving reduced nickel silicide contact resistance in strained n-FETs, where a pre-silicide Aluminum (Al) implant was introduced, and the Al profile was controlled/engineered by Carbon (C). C suppresses Al diffusion during silicidation, hence retaining high concentration of Al within the NiSi. Incorporating Al within NiSi reduces the Schottky barrier height for n-Si:C contact, leading to 18 % IOn improvement for Si:C S/D nFETs with no compromise on short channel effects.
    Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International 01/2011;

Publication Stats

1k Citations
294.59 Total Impact Points


  • 2011
    • Institute of Microelectronics
      Tumasik, Singapore
  • 1994–2011
    • National University of Singapore
      • Department of Electrical & Computer Engineering
      Singapore, Singapore
  • 2008
    • Georgia Institute of Technology
      • School of Electrical & Computer Engineering
      Atlanta, GA, United States