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ABSTRACT: The different hot-carrier degradation mechanisms of the lateral insulated-gate bipolar transistor on a silicon-on-insulator substrate (SOI-LIGBT) for different stress conditions have been experimentally investigated for the first time. For low V<sub>gs</sub> and high V<sub>ds</sub>, the hot hole injects and traps into the accumulation and the field oxide, particularly the bird's beak, which results in the decrease in the on-resistance R<sub>on</sub> at the early stress stage. It is interesting that the decrease level of R<sub>on</sub> in SOI-LIGBT is much more serious than that in the SOI laterally diffused metal-oxide-semiconductor with the same structure fully except for the doping type in the drain area. In addition, the buried oxide surface under the drain area also suffers from severe hot-carrier degradation. However, for high V<sub>gs</sub> and low V<sub>ds</sub>, only hot-electron injection into the gate oxide near the source side can be observed; there is no hot-carrier degradation to be found in both the field and buried oxides.
IEEE Transactions on Electron Devices 05/2011; · 2.32 Impact Factor
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ABSTRACT: In this paper, the p-type lateral extended drain MOS (pLEDMOS) transistor with thick gate oxide for plasma display panel (PDP) data driver ICs is developed. The following reliability issues have been discussed in detail: (1) hot-carrier degradation, (2) the contradiction between the parasitic bipolar junction transistor (BJT) punch-through phenomenon and the impurity segregation effect, (3) surface damage caused by the long-time diffusion process under high-temperature conditions, (4) creep behavior of the breakdown voltage and (5) the Kirk effect due to the high working current density. The improved methods for solving these reliability problems by optimizing the process and device architecture are also presented. The methods have also been verified by the technology computer-aided design (TCAD) simulations and experimental results.
Semiconductor Science and Technology 03/2011; 26(5):055001. · 1.72 Impact Factor
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ABSTRACT: A novel charge-imbalance termination region for high-voltage trench superjunction (SJ) vertical diffused MOSFETs (SJ-VDMOSs) is proposed and discussed in this letter. Its breakdown characteristics are investigated theoretically and experimentally. A simple and meaningful analytical-solution method is proposed, and it agrees with the simulation and experimental results. As a result, the novel imbalance termination can suppress the edge-drift potential more effectively than the conventional one in the off state. When the trench SJ-VDMOS was compared with a conventional termination structure of the same size, the device improved the breakdown voltage (BV) by about 8% using the proposed termination structure. Experimentally, a BV of 715 V was obtained in the trench SJ-VDMOS with a 35-μm trench on a 45-μm epitaxial layer and a 90- μm termination region.
IEEE Electron Device Letters 01/2011; · 2.85 Impact Factor
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Microelectronics Journal. 01/2011; 42:1169-1175.
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01/2010
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ABSTRACT: The degradations of p-type lateral extended drain MOS transistors with thick gate oxide are experimentally investigated. To decrease the hot-carrier degradation, two methods are proposed to optimize the drift region without additional processes. The novel structure is with a low doped boundary of the drift region and a drift region implanted at intervals by multi-windows, which will be helpful in reducing the electric field, reducing the degradations of electrical parameters correspondingly. The effects have been detailed analyzed by the CP measurements and TCAD simulations. Out of the simulations results, the length of the low doped boundary and the space between the doping windows of the sub-drifts are discussed, and their effects on the degradation induced by hot carriers has been investigated in detailed. An optimization structure is proposed for the first time.
Microelectronics Reliability. 01/2010;
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ABSTRACT: A low voltage MOSFET-only voltage reference using body effect and subthreshold operation is proposed in this paper. A temperature coefficient of 5 ppm/°C from -55°C to 90°C is achieved as the combined effects of: 1) a suppression of the temperature dependence of mobility; 2) a piecewise compensation of the temperature dependence of subthreshold slope parameter during the second half of temperature range. The voltage reference is designed in SMIC 0.13 ¿m CMOS process. It is able to operate at power supply voltage down to 760 mV and consumes a supply current of less than 1 ¿A at 90°C.
ASIC, 2009. ASICON '09. IEEE 8th International Conference on; 11/2009
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ABSTRACT: The degradations of p-type lateral extended drain MOS transistors with thick gate oxide are experimentally investigated. A novel structure is proposed with a low doped boundary of the drift region without additional process, which will be helpful in reducing the electric field, reducing the degradations of electrical parameters correspondingly. The effects have been detailed analyzed by the CP measurements and MEDICI simulations. Our of the simulations results, the length of the low doped boundary of the drift region is discussed and their effect on the degradation induced by hot carriers has been investigated. An optimization structure is proposed.
Physical and Failure Analysis of Integrated Circuits, 2009. IPFA 2009. 16th IEEE International Symposium on the; 08/2009
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IEICE Transactions. 01/2009; 92-C:1299-1303.
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Microelectronics Journal. 01/2009; 40:939-943.
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ABSTRACT: The anomalous hot-carrier degradation phenomenon is observed in a high voltage n-type lateral extended drain MOS (nLEDMOS) for different stress conditions. From the analysis of the electrical data and two-dimensional device simulations, a new hot-carrier degradation in a nLDMOS is presented. The electron and hole injection mechanism depends strongly on the stress conditions: at low Vgs, the degradation mechanism affecting hot carrier effect was due to both hot-hole injection in the field oxide and hot-electron injection in the gate oxide, and at high Vgs the electron injection becomes dominant. With the stress time increasing the hot carrier injection will reach saturation and the interface trap formation in the channel region takes over. A straightforward physical explanation of the observed effects is provided.
Microelectronics, 2008. MIEL 2008. 26th International Conference on; 06/2008
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Microelectronics Reliability. 01/2008; 48:1804-1808.
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ABSTRACT: This letter reports a low-cost and excellent latch-up protection technology for bulk-silicon scan driver ICs of shadow-mask plasma-display panel (SM-PDP) by integrating a 100-V lateral double-diffused (LD) MOS and a standard low-voltage (LV)-CMOS control circuit. The technology is implemented using an N+ guard ring in the LV-n-well, a P+ guard ring in the p-substrate near the LV-nMOS, and a deep high-voltage (HV)-n-well and a p-drift guard ring between the HV-nLDMOS and LV-CMOS circuits. The experiment results show that the latch-up in the LV-CMOS circuits is avoided when the scan ICs are applied with -340 V during the sustain periods.
IEEE Electron Device Letters 01/2008; · 2.85 Impact Factor
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ABSTRACT: The different on-resistance degradations of the p-type lateral extended drain MOS (pLEDMOS) transistor with thick gate oxide for different hot carrier stress conditions have been experimentally investigated for the first time. The difference results from the interface trap generation and the hot electron injection and trapping into the thick gate oxide and field oxide of the pLEDMOS transistor, which has been analyzed in detail using the MEDICI simulator.
IEEE Electron Device Letters 08/2007; · 2.85 Impact Factor
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ABSTRACT: A novel high-voltage (HV) CMOS IC technology using 25-μm-thick epitaxy layer based on 1.2-μm standard CMOS process for color plasma display panel (PDP) scan-driver ICs has been developed. In this technology, HV n-channel vertical double diffused MOS (nVDMOS), reduced surface field p-channel lateral double diffused MOS (pLDMOS), and the low-voltage CMOS (LVCMOS) are integrated together. The p<sup>+</sup>n junction isolation is used to isolate nVDMOS from the pLDMOS, LVCMOS, and other nVDMOSs. A novel level-shift circuit has also been suggested in the PDP scan-driver IC. The experimental results show that the breakdown voltages of the presented nVDMOS and pLDMOS both exceed 200V whether in the OFF or ON state. The rise and fall times of the proposed PDP scan-driver IC are about 270 and 50ns, respectively, which are two important performances to the high response speed of PDPs. The power consumption of the proposed PDP scan-driver IC with the novel level shift circuit has been reduced by about 20% compared with that of the PDP scan-driver IC with the conventional level shift circuit. Furthermore, the cost can be greatly saved using the presented bulk-silicon fabrication technology compared with the silicon-on-insulator technology.
IEEE Transactions on Electron Devices 05/2006; · 2.32 Impact Factor
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Microelectronics Reliability. 01/2006; 46:1001-1005.
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ABSTRACT: A high voltage CMOS IC technology by using 25μm thick epitaxy based on 1.2μm standard CMOS process has been developed. In this technology, LDMOS and VDMOS are fabricated together. Junction isolation is used to isolate VDMOS from LDMOS, low voltage CMOS, and other VDMOSs. Test results show that the rise time and the fall time of the output stage is about 45ns and 50ns, respectively. For the simplicity of the technology, the cost is saved.
Power Semiconductor Devices and ICs, 2005. Proceedings. ISPSD '05. The 17th International Symposium on; 06/2005
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Microelectronics Reliability. 01/2005; 45:185-190.
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ABSTRACT: In this paper, the surface electrical field distributions along the drift regions of the conventional LEDMOS, TPFP LEDMOS and M-TPFP LEDMOS were presented by MEDICI respectively. In terms of the analysis and discussion results on the changes of the electrical field peaks of the three high voltage LEDMOS, a method to improve the breakdown capability of the high voltage BS LEDMOS was given. The analysis results also proved that the metal wires crossed the LEDMOS wouldn't degrade the breakdown capability of the high voltage LEDMOS for the thick oxide layer.
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on; 11/2004
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ABSTRACT: For designing LDMOS, SOA is an important and complex parameter which is defined by current, voltage, waveform, pulse time, etc. In this paper, short-term and long-term factors that determine the SOA boundary are demonstrated. Methods to improve SOA are enumerated.
Microelectronics Journal.
