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IEICE Transactions. 01/2012; 95-D:392-402.
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ABSTRACT: In this paper, the p-type lateral extended drain MOS (pLEDMOS) transistor with thick gate oxide for plasma display panel (PDP) data driver ICs is developed. The following reliability issues have been discussed in detail: (1) hot-carrier degradation, (2) the contradiction between the parasitic bipolar junction transistor (BJT) punch-through phenomenon and the impurity segregation effect, (3) surface damage caused by the long-time diffusion process under high-temperature conditions, (4) creep behavior of the breakdown voltage and (5) the Kirk effect due to the high working current density. The improved methods for solving these reliability problems by optimizing the process and device architecture are also presented. The methods have also been verified by the technology computer-aided design (TCAD) simulations and experimental results.
Semiconductor Science and Technology 03/2011; 26(5):055001. · 1.72 Impact Factor
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Microelectronics Journal. 01/2011; 42:1169-1175.
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IEEE Trans. VLSI Syst. 01/2011; 19:857-868.
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01/2010
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ABSTRACT: The degradations of p-type lateral extended drain MOS transistors with thick gate oxide are experimentally investigated. To decrease the hot-carrier degradation, two methods are proposed to optimize the drift region without additional processes. The novel structure is with a low doped boundary of the drift region and a drift region implanted at intervals by multi-windows, which will be helpful in reducing the electric field, reducing the degradations of electrical parameters correspondingly. The effects have been detailed analyzed by the CP measurements and TCAD simulations. Out of the simulations results, the length of the low doped boundary and the space between the doping windows of the sub-drifts are discussed, and their effects on the degradation induced by hot carriers has been investigated in detailed. An optimization structure is proposed for the first time.
Microelectronics Reliability. 01/2010;
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ABSTRACT: The degradations of p-type lateral extended drain MOS transistors with thick gate oxide are experimentally investigated. A novel structure is proposed with a low doped boundary of the drift region without additional process, which will be helpful in reducing the electric field, reducing the degradations of electrical parameters correspondingly. The effects have been detailed analyzed by the CP measurements and MEDICI simulations. Our of the simulations results, the length of the low doped boundary of the drift region is discussed and their effect on the degradation induced by hot carriers has been investigated. An optimization structure is proposed.
Physical and Failure Analysis of Integrated Circuits, 2009. IPFA 2009. 16th IEEE International Symposium on the; 08/2009
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ABSTRACT: An area-efficient architecture for 2D DWT is proposed in this paper based on novel decomposed lifting scheme, where no data buffer is required to preserve and reorder the intermediate data between the row and column processor. Compared with the reported research, the proposed design could benefit from the reduction of internal memory size and the number of multipliers, adders and registers. The design was implemented for 2D 9/7 and 5/3 DWT in SMIC 0.18 mum CMOS logic fabrication with 15 K equivalent 2-input NAND gates under 150 MHz, which can accommodate up to 512times512 image size with 4 K bytes on-chip dual-port RAM.
Multimedia and Expo, 2009. ICME 2009. IEEE International Conference on; 08/2009
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Journal of Circuits, Systems, and Computers. 01/2009; 18:697-711.
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IEICE Transactions. 01/2009; 92-C:1299-1303.
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Microelectronics Journal. 01/2009; 40:939-943.
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ABSTRACT: The anomalous hot-carrier degradation phenomenon is observed in a high voltage n-type lateral extended drain MOS (nLEDMOS) for different stress conditions. From the analysis of the electrical data and two-dimensional device simulations, a new hot-carrier degradation in a nLDMOS is presented. The electron and hole injection mechanism depends strongly on the stress conditions: at low Vgs, the degradation mechanism affecting hot carrier effect was due to both hot-hole injection in the field oxide and hot-electron injection in the gate oxide, and at high Vgs the electron injection becomes dominant. With the stress time increasing the hot carrier injection will reach saturation and the interface trap formation in the channel region takes over. A straightforward physical explanation of the observed effects is provided.
Microelectronics, 2008. MIEL 2008. 26th International Conference on; 06/2008
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ABSTRACT: A low jitter All-Digital Phase-Locked Loop (ADPLL) used as a clock generator is designed. The Digital-Controlled Oscillator
(DCO) for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity
Function (ISF) analysis, an effective way is proposed to reduce the ADPLL’s jitter by the careful design of the sizes of the
inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process
with 1.8V supply voltage, occupies 0.046mm2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter
is 139ps when the DCO’s output frequency is 188MHz.
Journal of Electronics (China) 01/2008; 25(5):673-678.
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Microelectronics Reliability. 01/2008; 48:1804-1808.
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IEICE Transactions. 01/2008; 91-C:1971-1975.
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ABSTRACT: This letter reports a low-cost and excellent latch-up protection technology for bulk-silicon scan driver ICs of shadow-mask plasma-display panel (SM-PDP) by integrating a 100-V lateral double-diffused (LD) MOS and a standard low-voltage (LV)-CMOS control circuit. The technology is implemented using an N+ guard ring in the LV-n-well, a P+ guard ring in the p-substrate near the LV-nMOS, and a deep high-voltage (HV)-n-well and a p-drift guard ring between the HV-nLDMOS and LV-CMOS circuits. The experiment results show that the latch-up in the LV-CMOS circuits is avoided when the scan ICs are applied with -340 V during the sustain periods.
IEEE Electron Device Letters 01/2008; · 2.85 Impact Factor
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ABSTRACT: A well known problem of time-interleaved analog-to-digital converters is the matching between the channels of the converter. The random mismatch of components between the channels affects the accuracy of the converter especially for high-resolution converters. In this paper, a digital self-calibration is proposed based on least mean square (LMS) algorithm for canceling the offset and gain mismatches. And a global sampling clock using feed-forward compensates for the bottom-plate sampling skew. Simulations on the four-channel time-interleaved pipelined ADC shows that after calibration, the converter could attain 10-bit accuracy successfully.
ASIC, 2007. ASICON '07. 7th International Conference on; 11/2007
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ABSTRACT: System simulations seek to strike a balance between accuracy and performance. This paper elaborates on the realization of a system simulator. The SystemC-based platform provides the simulation environment for the target application and the cycle-accurate performance evaluation for the optimization methodology. Compared with the result of the actual prototyping simulation, the maximal evaluation error of the simulator is less than 0.02% and the simulating speed is 800 times faster than actual prototyping simulation.
ASIC, 2007. ASICON '07. 7th International Conference on; 11/2007
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ABSTRACT: The different on-resistance degradations of the p-type lateral extended drain MOS (pLEDMOS) transistor with thick gate oxide for different hot carrier stress conditions have been experimentally investigated for the first time. The difference results from the interface trap generation and the hot electron injection and trapping into the thick gate oxide and field oxide of the pLEDMOS transistor, which has been analyzed in detail using the MEDICI simulator.
IEEE Electron Device Letters 08/2007; · 2.85 Impact Factor
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ABSTRACT: A novel high-voltage (HV) CMOS IC technology using 25-μm-thick epitaxy layer based on 1.2-μm standard CMOS process for color plasma display panel (PDP) scan-driver ICs has been developed. In this technology, HV n-channel vertical double diffused MOS (nVDMOS), reduced surface field p-channel lateral double diffused MOS (pLDMOS), and the low-voltage CMOS (LVCMOS) are integrated together. The p<sup>+</sup>n junction isolation is used to isolate nVDMOS from the pLDMOS, LVCMOS, and other nVDMOSs. A novel level-shift circuit has also been suggested in the PDP scan-driver IC. The experimental results show that the breakdown voltages of the presented nVDMOS and pLDMOS both exceed 200V whether in the OFF or ON state. The rise and fall times of the proposed PDP scan-driver IC are about 270 and 50ns, respectively, which are two important performances to the high response speed of PDPs. The power consumption of the proposed PDP scan-driver IC with the novel level shift circuit has been reduced by about 20% compared with that of the PDP scan-driver IC with the conventional level shift circuit. Furthermore, the cost can be greatly saved using the presented bulk-silicon fabrication technology compared with the silicon-on-insulator technology.
IEEE Transactions on Electron Devices 05/2006; · 2.32 Impact Factor
