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ABSTRACT: Recent studies have shown that manufacturing costs and design complexities may delay the widespread use of high-κ/metal gate nanoscale CMOS technologies. This implies that traditional (non-high-κ/non-metal gate) ultra-thin oxide technologies will remain active due to economic factors for longer periods of time. Direct tunneling is a significant source of MOSFET gate current in these technologies. Its presence fundamentally alters MOSFET functionality by invalidating the simplifying design assumption of infinite gate resistance. Analog circuit solutions to its problems do not exist in the literature. This paper proposes design solutions that attempt to minimize, balance, and cancel the negative effects of direct tunneling on analog design in traditional ultra-thin oxide CMOS technologies. The proposed solutions re quire only ultra-thin oxide devices and are investigated in a 65-nm CMOS technology with a nominal V<sub>DD</sub> of 1 V and a physical oxide thickness of 1.25 nm.
Circuits and Systems I: Regular Papers, IEEE Transactions on 05/2011; · 1.97 Impact Factor
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ABSTRACT: In conclusion, this work investigated the BJT-like behavior of MOSFETs in a 65 nm CMOS technology with significant gate current. The results show that the effects of I<sub>G</sub> can be minimized at the expense of power, voltage headroom, and matching. Also, performance metrics similar to BJTs can be used, with caution, to monitor the impact of gate current on MOSFETs.
Semiconductor Device Research Symposium, 2009. ISDRS '09. International; 01/2010
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ABSTRACT: This paper presents an analytical model for CMOS logic propagation delay which includes the effect of power supply noise. Using the nth power law model of MOSFETs, two scenarios are addressed: self-induced power supply noise and globally-induced power supply noise. The analytical model is verified in simulation for both cases. The self-induced noise model matches simulation to within 0.36%. The globally-induced noise model matches simulation to within 5% for typical input rise time values and never more than 15% under extreme conditions
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on; 06/2006
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ABSTRACT: Extraction plays an important role in the performance of device models especially in the high frequency regime. The present day extraction techniques mostly use a grounded source or common source (CS) device configuration. The models extracted from the grounded source devices are then used for devices in other configurations in a circuit application. This leads to discrepancies in accurate prediction of the circuit performance. This work investigates, the applicability of the models extracted using CS for other device configurations. It was shown with the help of measured data, in the frequency range of 1-20 GHz, that the models extracted from CS configuration do not predict the performance of a device in common drain (CD) configuration. Based on the above observation, a universal gate impedance model that works for both CS and CD configurations for BSIM3v3 was developed. The gate impedance model was then extended to BSIM4 for both CS and CD configurations. The models for BSIM3v3 and BSIM4 are verified using simulations and compared with the measured data
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on; 06/2006
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ABSTRACT: One of the most challenging problems encountered in developing RF circuits is accurate prediction of MOS behavior at microwave signal and data frequencies. An attempt is made in this work to accurately model the device input impedance for the 1-20-GHz frequency range. The effect of device length and single-leg width on the input impedance is studied with the aid of extensive measured data obtained from devices built in 0.11-μm and 0.18-μm technologies. The measured data illustrates that the device input impedance has a nonlinear frequency dependency. It is also shown that this variation in input impedance is a result of gate poly-silicon depletion, which can be modeled by an external RC network connected at the gate of the device. Excellent agreement between the simulation results and the measured data validates the model in the device active region.
IEEE Microwave and Wireless Components Letters 06/2006; · 1.72 Impact Factor
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ABSTRACT: The input match of RF front-end circuitry can degrade significantly due to process faults and parasitic package inductances at its input pad. The proposed technique ascertains the input match frequency of the circuit by using a built-in self-test (BiST) structure, determines the frequency interval by which it needs to be shifted to restore it to the desired value, and then feeds back a digital word to the low-noise amplifier (LNA), which adaptively corrects its input-match in real-time. The circuitry presented in the paper offers the advantages of low power overheads (the circuits can be powered off when not in use), robustness, no requirements of digital signal processing cores or processors, and fast calibration times (less than 30 μs). This proof of concept is demonstrated by designing a cascode LNA and the complete self-calibration circuit in IBM 0.25-μm CMOS RF process.
Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2006; · 1.41 Impact Factor
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ABSTRACT: Accurate prediction of multi-GHz CML dependency on data run-time variation requires precise device models at those frequencies. Inconsistencies caused in the CML by run-time variations of the input data are clearly demonstrated. Further, an accurate RF MOSFET model that can be dynamically changed to adapt to the input data stream variations is implemented. This model is used to simulate a CML buffer, where symmetrical and asymmetrical variations in the data stream run-length are considered. The simulation results show that the data run-length variations can degrade the buffer output by as much as 40%.
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on; 06/2005
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ABSTRACT: In this paper, we present the impact of both process and dimensional scaling on input loss (S<sub>11</sub>) prediction of MOSFET's at GHz frequencies. We study the distributed gate effect, the non-quasi static effect, and report a drop in the resistive component of S<sub>11</sub> for larger fingered devices at high frequencies (> 5 GHz). We identify the boundary at which such effects start dominating. A modification to the existing lumped model is presented that tracks this effect with high accuracy. The impact of oxide thickness on S<sub>11</sub> in the same process and across two different processes is also presented. The study was validated with the fabrication of an extensive set of RF dimensioned transistors in LSI Logic's 0.18 μm and 0.11 μm processes, across five different wafers.
VLSI Design, 2005. 18th International Conference on; 02/2005
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ABSTRACT: This paper presents an ultra-fast built in self test (BiST) approach for RF low noise amplifiers. The technique uses test inputs of moderate precision and low overhead base-band circuitry to quantify various functional specifications in the LNA such as input/output match, power gain and linearity. The total self-test time for all these parameters is 15μs, which is several orders of magnitude improvement over existing test techniques. The BiST circuitry described presents low real estate and power overheads and does not require the presence of DSP cores to achieve self-test. The technique has been demonstrated for a 1.9GHz cascode LNA designed in the 0.25 micron IBM 6RF process.
VLSI Design, 2005. 18th International Conference on; 02/2005
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ABSTRACT: The input match of low noise amplifiers can degrade significantly due to process faults and the parasitic package inductances at its input pad. These inductances have wide tolerances and are difficult to co-design for. This paper presents a self-correction methodology that will go beyond BIST systems by ascertaining the input match frequency and dynamically re-aligning it, thus rendering the input match fault and package tolerant. The proposed two-tonal approach depends only on the difference of two signals that pass through the same sensing circuitry. Consequently, it is inherently insensitive to process, power supply and temperature variations. Coupled with the fact that the majority of the signal processing occurs in the baseband/DC domain, complexity and precision demands are highly lenient. We present simple, low-precision circuitry designed in IBM 0.25 μm CMOS RF process with low power and real-estate overheads, no DSP cores or processors and fast correction times of less than 30 μs. To the authors' knowledge, this paper represents the first ever attempt at self correction of integrated RF front-end circuitry.
Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings. 19th IEEE International Symposium on; 11/2004
