I. Bostan

Publications (7)0 Total impact

• Conference Proceeding: Design of programmable cellular automata based cipher scheme

  P. Anghelescu, S. Ionita, I. Bostan
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  ABSTRACT: This paper presents an originally encryption system implemented on a structure of hybrid additive programmable cellular automata (HAPCA). As the development of cellular automata (CA) applications is generally an experimental effort, the research implies the exploration through simulation of the huge space of cellular automata local rules and global states. The encryption and decryption modules are identically and the cryptosystem is featured by its large key space and high speed due to cellular automata's parallel information processing. The method supports both software and hardware implementation. In this paper we present a fully functional software application for the data encryption of Yahoo messenger conversations.
  Nature & Biologically Inspired Computing, 2009. NaBIC 2009. World Congress on; 01/2010
• Conference Proceeding: Systemic design for integrated digital circuit structures

  V. Ionescu, I. Bostan, L. Ionescu
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  ABSTRACT: The design of digital structures that are implemented in FPGAs or ASICs is subject to many constraints. This work proposes that systemic design should be used to optimize area/speed tradeoffs in simple digital structures (adders). Systemic approach in complex problem solving allows the analysis and synthesis of objects of different nature and complexity from a holistic point of view, considering the initial complex factors for each system. Although there are a variety of adder circuits (Ripple Carry Adder; Carry Skip Adder; Carry Increment Adder; Sklansky Adder; Kogge & Stone Adder), following the systemic design, optimum structures are obtained, given the initial complex constraints.
  Semiconductor Conference, 2004. CAS 2004 Proceedings. 2004 International; 11/2004
• Conference Proceeding: Design, microfabrication and testing of acceleration microtransducers for automotive applications

  B. Firtat, C. Moldovan, N. Dumbravescu, S. Ionita, I. Bostan
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  ABSTRACT: An original new design for manufacturing a piezoresistive micro-accelerometer is presented. As resulted from the computer simulations, and, after that, from the functional testing of the accelerometer, the new design provides a good response from the sensor, which reflects in its sensitivity. The device was manufactured by silicon bulk micromachining, using standard microsystems technology. The tests results showed a heterogeneous structure, with good response signals.
  Semiconductor Conference, 2004. CAS 2004 Proceedings. 2004 International; 11/2004
• Conference Proceeding: Systematic odometry errors compensation for mobile robot positioning

  I. Bostan, I. Lita, E. Franti, M. Dascalu, C. Moldovan, S. Goschin
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  ABSTRACT: This paper presents some aspects about measurement and compensation of the systematic odometry errors for differential drive platforms. The experimental results obtained by running two different UMBmark tests show that systematic calibration can reduce systematic odometry errors more than 10 times.
  CADSM 2003. The Experience of Designing and Application of CAD Systems in Microelectronics. Proceedings of the VIIth International Conference; 03/2003
• Conference Proceeding: Evolutionary computing systems for obstacle avoidance

  I. Bostan, E. Franti, M. Dascalu, S. Goschin
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  ABSTRACT: In this paper we present two neuronal network architectures to perform the task of obstacle avoidance for a little mobile robot named Khepera, which has 8 infrared proximity detectors and two independent motors. The first one used Hebbian learning for weight adaptation and the second one use evolutionary weight selection. The experiments are only simulated.
  Semiconductor Conference, 2003. CAS 2003. International;
• Conference Proceeding: FPGA implementation of a deterministic bit-stream neuron

  I. Bostan, V. Ionescu, C. Moldovan
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  ABSTRACT: This paper presents a digital hardware implementation of a deterministic Bit-Stream Artificial Neuron (AN) with ten inputs. The design was made to be implemented in a FPGA device for a minimal hardware requirement. The simulation for XCV3200 Virtex FPGA device, showed the possibility to place around 200 neurons (including the extra logic required to run the networks). As each neuron has ten connections this means that it will be possible to place a network with 2000 weights.
  Semiconductor Conference, 2003. CAS 2003. International;
• Conference Proceeding: FPGA implementation of a Boolean neuronal network

  L. Ionescu, I. Bostan, V. Ionescu
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  ABSTRACT: This paper presents the model of Boolean neuronal network. This model of neuron considers inputs and outputs to be binary and the weight controls function to be the multiplexer of some bases binary relations. The neuron body is a threshold gate which can implement different functions. The neuron was designed using a "multiplexer" of Boolean functions, a random hardware circuit for weight and a majority circuit for the body. The network was designed using top-level structural description with neuron as an object and it was implemented in a FPGA structure.
  Semiconductor Conference, 2003. CAS 2003. International;