A.V.Y. Thean,
T. White,
M. Sadaka,
L. McCormick,
M. Ramon,
R. Mora, P. Beckage,
M. Canonico,
X.-D. Wang,
S. Zollner, [......],
C.H. Chang,
Y.H. Chiu,
H.C. Tuan,
Y.C. See,
M.S. Liang,
Y.C. Sun,
I. Cayrefourcq,
F. Metral,
M. Kennard,
C. Mazure
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ABSTRACT: This paper describes the performance of multiple-V<sub>T</sub>, Triple-gate oxide SC-SSOI CMOS realized with Freescale's high-performance silicon-on-insulator (HiPerMOS-SOI) and SOITEC's advanced wafer-bonding technology. The thermal stability of wafer-bonded strained substrate, the beneficial impact of biaxial strain on gate-leakage and SC-SSOI enhanced SRAM bitcell operation are demonstrated for the first time. In-addition, the important scaling issues due to parasitic resistance and channel strain engineering are identified.
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005