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K. Agawa,
H. Majima,
H. Kobayashi,
M. Koizumi,
S. Ishizuka,
T. Nagano,
M. Arai,
Y. Shimizu,
G. Urakawa,
N. Itoh,
M. Hamada,
N. Otsuka
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ABSTRACT: A 2.4 GHz 0.13 μm CMOS transceiver achieving high RX sensitivity and high-quality TX signals between -40°C and +90°C is presented. A low-IF receiver and direct-conversion transmitter architecture is employed. A temperature compensated receiver chain including LNA achieves a sensitivity of -89.6 dBm even in the worst environmental condition. Linearity optimization for the transmitter chain including a variable biasing circuit in PA reduces the second harmonics of TX signals so that it suppresses the VCO pulling and keeps the carrier frequency drift within 18 kHz.
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE; 10/2007
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ABSTRACT: An automatic amplitude control circuit to minimize the phase noise of a LC-VCO is proposed and implemented by a 0.18-μm CMOS process. The phase noise lower than -90dBc/Hz at 100kHz offset is achieved over a wide tuning range (from 2.2GHz to 2.8GHz) under large process (ΔV<sub>th</sub> = ±100mV), temperature (from ∼35°C to 85°C), and power supply (from 1.8V to 3V) variations.
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005; 10/2005
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ABSTRACT: A 4th-order complex bandpass filter (BPF) with a tunable center frequency is designed and fabricated in a 0.13 μm CMOS technology. The transfer function is changeable dynamically. The passband center frequency can be set to 0 Hz, 1 MHz, 1.5 MHz and 2 MHz so that the filter can work as a complex BPF in the receiver path and as a LPF in the transmit path. An opamp-RC filter is used to obtain a wide dynamic range. The filter operates with the supply voltage as low as 1.2 V. The input referred noise for 1.4 MHz band width is 53 μVrms. IIP3 and the image rejection ratio at 1.5 MHz is 25.2 dBm and 52 dB, respectively.
Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European; 10/2005
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ABSTRACT: A single-chip low-IF transmitter for the Bluetooth enhanced data rate (max. 3Mbps) was fabricated in 0.18-μm CMOS process. A quantitative study on the relation between the VCO pulling, intermediate frequency, and the linearity of the PA shows that the 1MHz-IF is the best solution. By a digital DC offset cancellation and I/Q mismatch trimming techniques, the LO and image signal leakages are suppressed below -40dBc and -50dBc, respectively.
VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
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ABSTRACT: This paper describes the effect of digital noise on RF circuits on the single chip Bluetooth SoC. Low frequency components in the digital noise, generated by I/O circuits accessing to an external memory, are found to be converted to the phase noise as the spurs of voltage controlled oscillator (VCO). The spurs bring the performance degradation of wireless communications systems. To manage the gain of the VCO and the coupling coefficient is shown to be a key to mitigate the performance degradations.
Radio Frequency integrated Circuits (RFIC) Symposium, 2005. Digest of Papers. 2005 IEEE; 07/2005
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T. Tanzawa,
H. Shibayama,
R. Terauchi,
K. Hisano,
H. Ishikuro,
S. Kousai,
H. Kobayashi,
H. Majima,
T. Takayama, K. Agawa,
M. Koizumi,
F. Hatori
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ABSTRACT: The frequency drift of an open-loop PLL is an issue for direct modulation applications such as Bluetooth transceivers. The drift mainly comes from the temperature variation of the VCO during the TX operation. In this paper, we propose the optimum location of the VCO, considering the temperature gradient through full-chip thermal analysis. Moreover, a novel temperature-compensated VCO by employing a new biasing scheme is proposed. The combination of these two techniques enables power reduction of the transmitter by 33% without sacrificing performance.
Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004; 11/2004
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ABSTRACT: A bitline leakage current of an SRAM, induced by leakage current
of the transmission transistors in the cells that are associated with
the bitline, increases as the threshold voltage (V<sub>TH</sub>) of the
transistors is reduced for high performance at low power-supply voltage
(V<sub>DD</sub>). The increased bitline leakage causes slow or incorrect
read/write operation of an SRAM because the leakage current acts as
noise current for a sense amplifier. In this paper, the problem has been
solved from a circuitry point of view, and the scheme which detects the
bitline leakage current in a precharge cycle and compensates for it
during a read/write cycle is proposed. Employing this scheme, the SRAM
with 360-μA bitline leakage current can perform a read/write
operation at the same speed as one that has no bitline leakage current.
This enables a 0.1-V reduction in V<sub>TH</sub>, and keeps the V<sub>TH
</sub> and delay scalability of a high-performance SRAM in technology
progress. An experimental 8-Kb SRAM with 256 rows is fabricated in a
0.25-μm CMOS technology, which demonstrates the effectiveness of the
scheme
IEEE Journal of Solid-State Circuits 06/2001; · 3.23 Impact Factor
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ABSTRACT: The bit-line leakage current of an SRAM, induced by transistor
leakage at low V<sub>DD</sub> and dependent on cell data associated with
the bit-line, is detected in a pre-charge cycle and compensated for
during a read/write cycle. By this scheme, V<sub>th</sub> can be lowered
to 0.23 V<sub>DD</sub> in a 0.07 μm/1.0 V CMOS, as it was before,
keeping V<sub>th</sub> and delay scalability of the high-speed
SRAM
VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on; 02/2000
