Guoqing Chen

University of Rochester, Rochester, New York, United States

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Publications (21)10.5 Total impact

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    Guoqing Chen, Eby G. Friedman
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    ABSTRACT: With higher operating frequencies, transmission lines are required to model global on- chip interconnects. In this paper, an accurate and efficient solution for the transient response at the far end of a transmission line based on a direct pole extraction of the system is proposed. Closed form expressions of the poles are developed for two special interconnect systems: an RC interconnect and an RLC interconnect with zero driver resistance. By performing a system conversion, the poles of an interconnect system with general circuit parameters are solved. The Newton-Raphson method is used to further improve the accuracy of the poles. Based on these poles, closed form expressions for the step and ramp response are determined. Higher accuracy can be obtained with additional pairs of poles. The computational complexity of the model is proportional to the number of pole pairs. With two pairs of poles, the average error of the 50% delay is 1% as compared with Spectre simulations. With ten pairs of poles, the average error of the 10%-to-90% rise time and the overshoots is 2% and 1.9%, respectively. Frequency dependent effects are also successfully included in the proposed method and excellent match is observed between the proposed model and Spectre simulations.
    Journal of Circuits System and Computers 01/2009; 18:1263-1285. · 0.24 Impact Factor
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    Guoqing Chen, E.G. Friedman
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    ABSTRACT: An accurate and efficient solution for the transient response at the far end of a transmission line is proposed in this paper. Unlike approximating the poles by truncating the transfer function or matching moments, the exact poles of an interconnect system are analytically extracted. Excellent match is observed between the proposed method and Spectre simulations. With two pairs of poles, the average error for the 50% delay is 1%. Higher accuracy can be obtained with additional pairs of poles. The computational complexity of the model is proportional to the number of pole pairs.
    Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on; 06/2008
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    Guoqing Chen, E.G. Friedman
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    ABSTRACT: Interconnect resistance and inductance shield part of the load capacitance, resulting in a faster voltage transition at the output of the driver. Ignoring this shielding effect may induce significant error when estimating short-circuit power. In order to capture this shielding effect, an effective capacitance of a distributed RLC load is presented for accurately estimating the short-circuit power. The proposed method has been verified with Cadence Spectre simulations. The average error of the short-circuit power obtained with the effective capacitance is less than 7% for the example circuits as compared with an RLC model. This effective capacitance can be used in look-up tables or in empirical -factor expressions to estimate short-circuit power.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 02/2008; · 1.33 Impact Factor
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    Guoqing Chen, Eby G. Friedman
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2008; 55-II:26-30. · 1.33 Impact Factor
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    ABSTRACT: Interconnect has become a primary bottleneck in the integrated circuit design process. As CMOS technology is scaled, the design requirements of delay, power, bandwidth, and noise due to the on-chip interconnects have become more stringent. New design challenges are continuously emerging, such as delay uncertainty induced by process and environmental variations. It has become increasingly difficult for conventional copper interconnect to satisfy these design requirements. On-chip optical interconnect has been considered as a potential substitute for electrical interconnect. In this paper, predictions of the performance of CMOS compatible optical devices are made based on current state-of-the-art optical technologies. Electrical and optical interconnects are compared for various design criteria based on these predictions. The critical dimensions beyond which optical interconnect becomes advantageous over electrical interconnect are shown to be approximately one-tenth of the chip edge length at the 22 nm technology node.
    Integration, the VLSI Journal. 01/2007;
  • Integration. 01/2007; 40:434-446.
  • Source
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    ABSTRACT: Interconnect has become a primary bottleneck in the integrated circuit design process. As CMOS technology is scaled, the design requirements of delay, power, bandwidth, and noise due to the on-chip interconnects have become increasingly stringent. New design challenges are continuously emerging, such as delay uncertainty induced by process and environmental variations. It has become increasingly difficult for conventional copper interconnect to satisfy a variety of design requirements. On-chip optical interconnect has been considered as a potential partial substitute for electrical interconnect. In this paper, predictions of the performance of CMOS compatible optical devices are made based on current state-of-the-art optical technologies. Based on these predictions, the delay uncertainty in electrical and optical interconnects is analyzed, and shown to affect both the latency and bandwidth of the interconnect. The two interconnects are also compared for latency, power, and bandwidth density.
    01/2007;
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    ABSTRACT: We introduce a semi-analytical model of capacitor-based electro-optical modulators. By applying this model, the performance dependence on the primary device parameters can be analyzed and a set of design rules has been developed.
    10/2006;
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    ABSTRACT: As CMOS technology is scaled, it has become increasingly difficult for conventional copper interconnect to satisfy different design requirements. On-chip optical interconnect has been considered as a potential substitute for electrical interconnect. In this paper, predictions of the performance of CMOS compatible optical devices are made based on current state-of-art optical technologies. Based on these predictions, electrical and optical interconnects are compared for delay uncertainty, latency, power, and bandwidth density
    Interconnect Technology Conference, 2006 International; 07/2006
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    Guoqing Chen, E.G. Friedman
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    ABSTRACT: An effective capacitance of a distributed RLC load for estimating short-circuit power is presented in this paper. Both resistive and inductive shielding effects of interconnects are considered and no iterations are required to determine the effective capacitance. The proposed method has been verified with Cadence Spectre. For a single switching input, the average error of the short-circuit power obtained with the effective capacitance is less than 2% for the example circuits as compared with an RLC pi model. The proposed method can be used in look-up table or k-factor based models to estimate short-circuit power dissipation in CMOS gates with complex interconnects
    Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on; 06/2006
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    Guoqing Chen, E.G. Friedman
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    ABSTRACT: Interconnect plays an increasingly important role in deep-submicrometer very large scale integrated technologies. Multiple design criteria are considered in interconnect design, such as delay, power, and bandwidth. In this paper, a repeater insertion methodology is presented for achieving the minimum power in an RC interconnect while satisfying delay and bandwidth constraints. These constraints determine a design space for the number and size of the repeaters. The minimum power is shown to occur at the edge of the design space. With delay constraints, closed form solutions for the minimum power are developed, where the average error is 7% as compared with SPICE. With bandwidth constraints, the minimum power can be achieved with minimum-sized repeaters. The effects of inductance on the delay, bandwidth, and power of an RLC interconnect with repeaters are also analyzed. By including inductance, the minimum interconnect power under a delay or bandwidth constraint decreases as compared with an RC interconnect.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 03/2006; · 1.22 Impact Factor
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    Guoqing Chen, Eby G. Friedman
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    ABSTRACT: Interconnect plays an increasingly important role in deep-submicrometer very large scale integrated technologies. Multiple design criteria are considered in interconnect design, such as delay, power, and bandwidth. In this paper, a repeater insertion methodology is presented for achieving the minimum power in an RC interconnect while satisfying delay and bandwidth constraints. These constraints determine a design space for the number and size of the repeaters. The minimum power is shown to occur at the edge of the design space. With delay constraints, closed form solutions for the minimum power are developed, where the average error is 7% as compared with SPICE. With bandwidth constraints, the minimum power can be achieved with minimum-sized repeaters. The effects of inductance on the delay, bandwidth, and power of an RLC interconnect with repeaters are also analyzed. By including inductance, the minimum interconnect power under a delay or bandwidth constraint decreases as compared with an RC interconnect.
    IEEE Trans. VLSI Syst. 01/2006; 14:161-172.
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    ABSTRACT: Intrachip optical interconnects can outperform electrical wires but the required parameters for optical components are yet unknown. Here the ITRS is used as a reference point to derive the requirements that optical components must meet.
    Group IV Photonics, 2005. 2nd IEEE International Conference on; 10/2005
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    Guoqing Chen, E.G. Friedman
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    ABSTRACT: Based on a Fourier series analysis, an analytic interconnect model is presented which is suitable for periodic signals, such as a clock signal. In this model, the far end time domain waveform is approximated by the summation of several sinusoids. Closed form solutions of the 50% delay are provided when the fifth and higher harmonies are ignored. The model is applied to distributed interconnect trees and multiple coupled interconnects. Good accuracy is observed between the model and SPICE simulations. The computational complexity of the model is linear with the number of harmonies.
    Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on; 06/2005
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    ABSTRACT: The interconnect has become a primary bottleneck in integrated circuit design. As CMOS technology is scaled, it will become increasingly difficult for conventional copper interconnect to satisfy the design requirements of delay, power, bandwidth, and noise. On-chip optical interconnect is therefore being considered as a potential substitute for electrical interconnect. Based on predictions of optical device development, electrical and optical interconnects are compared for various design criteria. The critical dimensions beyond which optical interconnect becomes advantageous over electrical interconnect at the 22 nm technology node are approximately one tenth of the chip edge length.
    Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on; 06/2005
  • Source
    Guoqing Chen, E.G. Friedman
    [Show abstract] [Hide abstract]
    ABSTRACT: Interconnects play an increasingly important role in deep submicrometer VLSI technologies. Multiple design criteria are considered in interconnect design, such as delay, power, and bandwidth. The effects of inductance on the delay, bandwidth, and power of an RLC interconnect with repeaters are analyzed. A repeater insertion methodology is presented for achieving the minimum power in an RLC interconnect while satisfying delay and bandwidth constraints. By including inductance, the minimum interconnect power under a delay and/or bandwidth constraint decreases as compared with an RC interconnect.
    Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on; 06/2005
  • Source
    Guoqing Chen, E.G. Friedman
    [Show abstract] [Hide abstract]
    ABSTRACT: Based on a Fourier series analysis, an analytic interconnect model is presented which is suitable for periodic signals, such as a clock signal. In this model, the far-end time-domain waveform is approximated by the summation of several sinusoids. Closed-form solutions of the 50% delay and overshoots/undershoots are provided when the fifth and higher order harmonics are ignored. Good accuracy is observed between the model and SPICE simulations. The model is applied to resistance-capacitance-inductance interconnect trees and the computational complexity of the model is linear with the size of the tree and the model order. The tree model is shown to be an effective method to analyze clock distribution networks. The single interconnect model is also extended to coupled multi-interconnect systems to analyze crosstalk noise and a general waveform solution is obtained. It is noted that in addition to the transition time, the period of the aggressor signal also has a significant effect on the crosstalk noise.
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 03/2005; · 1.09 Impact Factor
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    ABSTRACT: The relentless pursuit of Moore's Law by the semiconductor industry has yielded signican t in- creases in performance, but at the cost of greater power dissipation. As CMOS technology continues to scale, increasing power densities, or \hot spots," particularly in dense logic structures, may limit fre- quencies below projected targets in order to avoid circuit malfunction. A solution to this problem is to separate the hot spots by interleaving these units with cooler cache banks. This approach, how- ever, increases the distance among processing func- tions, which can signican tly degrade performance. While eort is made to localize communication as much as possible, global communication cannot be completely avoided, particularly in parallel appli- cations. In this paper, the use of silicon-based on-chip optical interconnects is investigated for minimizing the performance gap created by separating process- ing functions due to thermal constraints. Mod- els of optical components are presented, and used to connect the common front-end with the dis- tributed back-ends of a large-scale Clustered Multi- Threaded (CMT) processor. A signican t reduc- tion in thermal constraints (translated into an in- crease in clock frequency), combined with improved instructions per cycle (IPC), is demonstrated over a conventional all-electrical system.
    01/2005;
  • Source
    Guoqing Chen, Eby G. Friedman
    [Show abstract] [Hide abstract]
    ABSTRACT: Based on a Fourier series analysis, an analytic interconnect model is presented which is suitable for periodic signals, such as a clock signal. In this model, the far-end time-domain waveform is approximated by the summation of several sinusoids. Closed-form solutions of the 50% delay and overshoots/undershoots are provided when the fifth and higher order harmonics are ignored. Good accuracy is observed between the model and SPICE simulations. The model is applied to resistance-capacitance-inductance interconnect trees and the computational complexity of the model is linear with the size of the tree and the model order. The tree model is shown to be an effective method to analyze clock distribution networks. The single interconnect model is also extended to coupled multi-interconnect systems to analyze crosstalk noise and a general waveform solution is obtained. It is noted that in addition to the transition time, the period of the aggressor signal also has a significant effect on the crosstalk noise.
    IEEE Trans. on CAD of Integrated Circuits and Systems. 01/2005; 24:170-183.
  • The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings; 01/2005