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ABSTRACT: The surging complexity of modern embedded systems has been imposing challenges to designers since last decade. It is generally agreed that an approach to taming the complexity is to properly raise the level of abstraction to that of system-level designs. The Unified Modelling Language (UML) is considered appropriate to specify abstract systems. To support the gap between UML and low level hardware descriptions, a few pilot tools and methodologies were proposed by both the EDA community and the academia. However, these tools either lack support for cycle accurate system specifications in UML or ignore the efficiency issue in cycle accurate system specifications based on UML. In this paper, an improved method is proposed to efficiently specify systems at cycle accuracy by significantly simplifying clock control modelling. This method is further supported by an improved translator to convert UML 2.0 specifications into executable SystemC descriptions. We believe that our method would be a significant contribution to the electronic system level (ESL) tools.
Intelligent Pervasive Computing, 2007. IPC. The 2007 International Conference on; 11/2007
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ABSTRACT: In the recent years, multi-core processors prove their extensive use in the area of System-on-Chip (SoC) on a single chip. This paper proposes a methodology and implements a multi-core simulator. The multi-core simulator is based on SimpleScalar integrated with SystemC framework, which deals with communication and synchronization among different processing modules. A shared memory scheme is introduced for inter-core communication with a set of shared memory access instructions and communicationmethods. A synchronization mechanism, which only switches the simulation component when communication occurs, is proposed for efficiency. Experiments prove that our simulator can correctly simulate the behavior of a multi-core system and demonstrate a high performance on Linux PC platforms.
Advanced Information Networking and Applications Workshops, 2007, AINAW '07. 21st International Conference on; 06/2007
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Emerging Directions in Embedded and Ubiquitous Computing, EUC 2006 Workshops: NCUS, SecUbiq, USN, TRUST, ESO, and MSA, Seoul, Korea, August 1-4, 2006, Proceedings; 01/2006
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Emerging Directions in Embedded and Ubiquitous Computing, EUC 2006 Workshops: NCUS, SecUbiq, USN, TRUST, ESO, and MSA, Seoul, Korea, August 1-4, 2006, Proceedings; 01/2006
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ABSTRACT: Circuit testing is the most significant cost in modern chip design and production. Due to the complexity in terms of millions of gates, manufacturers often have to truncate test patterns to make the testing feasible on ATEs with limited capacities. In this paper, we present a novel approach to this challenge by run-time coordinating the algorithm and ATE. A unique combination of a #SAT solver, checksum computation and frame testing enables the efficient incremental testing. Unlike checksums from the communication domain which can only detect the existence of stuck-at faults, our approach differentiates by also locating them. In our experimental results, our method further demonstrates a shorter testing time.
Embedded and Real-Time Computing Systems and Applications, 2005. Proceedings. 11th IEEE International Conference on; 09/2005
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ABSTRACT: While enabling fast implementation and reconfiguration of stream applications, programmable stream processors expose issues of incompatibility and lack of adoption in existing stream modeling languages. To address them we describe a design approach in which specifications are captured in UML 2.0, and automatically translated into SystemC models consisting of simulators and synthesizable code under proper style constraints. As an application case, we explain real time stream processor specifications using new UML 2.0 notations. Then we expound how our translator generates SystemC models and includes additional hardware details. Verifications are made during UML execution as well as assertions in SystemC. The case study demonstrates the feasibility of fast specifications, modifications and generation of real time stream processor designs.
Embedded and Real-Time Computing Systems and Applications, 2005. Proceedings. 11th IEEE International Conference on; 09/2005
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ABSTRACT: On current superscalar processors, performance and power issues cannot be decoupled for designers. Extensive simulations are usually required to meet both power and performance constraints. This paper describes an integrated performance and power analytical model. The model's performance and power results are in good agreement with detailed simulations, previous models and physically measured results. For designers, the model enables quick and flexible explorations into a subset of even entire huge parameter space of more than 15 workload and architectural parameters plus leakage power, feature sizes, clock and voltage.
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific; 02/2005
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ABSTRACT: Clocking is an essential component of any embedded system design. However, traditional design techniques are either short of clocking support or too complex for users. The Unified Modeling Language (UML) has been proposed as design tool in real time system design, but the clocking semantics has not been properly dealt with. In this paper, we will present our experience of using UML to design a clocked system. In particular, UML is used to model the digital down converter, an essential component of software radios. Our tool chain automatically generates the simulation as well as synthesizes the final implementation.
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific; 02/2005
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Fifth International Conference on Computer and Information Technology (CIT 2005), 21-23 September 2005, Shanghai, China; 01/2005
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ABSTRACT: We present an analytical framework to identify the tradeoffs and performance impacts associated with different SoC platform configurations in the specific context of implementing multimedia applications. "Configurations" in this case might include sizes of different on-chip buffers and scheduling mechanisms (or associated parameters) implemented on the different processing elements of the platform. Identifying such tradeoffs is difficult because of the bursty nature of on-chip traffic arising out of multimedia processing and the high variability in their execution requirements, which result in a highly irregular design space. We show that this irregularity in the design space can be precisely captured using an abstraction called variability characterization curves.
Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004. International Conference on; 10/2004
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Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004, Stockholm, Sweden, September 8-10, 2004; 01/2004
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ABSTRACT: As process technology scales down, power wall starts to hinder improvements in processor performance. Performance optimization
has to proceed under a power constraint. The co-optimization requires exploration into a huge design space containing both
performance and power factors, whose size is over costly for extensive traditional simulations. This paper describes a unified
model covering both performance and power. The model consists of workload parameters, architectural parameters plus corresponding
power parameters with a good degree of accuracy compared with physical processors and simulators. We apply the model to the
problem of co-optimizing the power and performance. Concrete insights into the tradeoffs of designs for performance and power
are obtained in the process of co-optimization.
01/1970: pages 868-878;
