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ABSTRACT: Operation in the subthreshold region most often is synonymous to minimum-energy operation. Yet, the penalty in performance is huge. In this paper, we explore how design in the moderate inversion region helps to recover some of that lost performance, while staying quite close to the minimum-energy point. An energy-delay modeling framework that extends over the weak, moderate, and strong inversion regions is developed. The impact of activity and design parameters such as supply voltage and transistor sizing on the energy and performance in this operational region is derived. The quantitative benefits of operating in near-threshold region are established using some simple examples. The paper shows that a 20% increase in energy from the minimum-energy point gives back ten times in performance. Based on these observations, a pass-transistor based logic family that excels in this operational region is introduced. The logic family operates most of its logic in the above-threshold mode (using low-threshold transistors), yet containing leakage to only those in subthreshold. Operation below minimum-energy point of CMOS is demonstrated. In leakage-dominated ultralow-power designs, time-multiplexing will be shown to yield not only area, but also energy reduction due to lower leakage. Finally, the paper demonstrates the use of ultralow-power design techniques in chip synthesis.
Proceedings of the IEEE 03/2010; · 6.81 Impact Factor
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ABSTRACT: This paper presents the design and implementation of a low-energy asynchronous logic topology using sense amplifier-based pass transistor logic (SAPTL). The SAPTL structure can realize very low energy computation by using low-leakage pass transistor networks at low supply voltages. The introduction of asynchronous operation in SAPTL further improves energy-delay performance without a significant increase in hardware complexity. We show two different self-timed approaches: 1) the bundled data and 2) the dual-rail handshaking protocol. The proposed self-timed SAPTL architectures provide robust and efficient asynchronous computation using a glitch-free protocol to avoid possible dynamic timing hazards. Simulation and measurement results show that the self-timed SAPTL with dual-rail protocol exhibits energy-delay characteristics better than synchronous and bundled data self-timed approaches in 90-nm CMOS.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 08/2009; · 1.22 Impact Factor
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ABSTRACT: This paper presents the design and implementation of a low energy asynchronous logic architecture using sense amplifier-based pass transistor logic (SAPTL). The SAPTL structure can realize very low energy computation by using low leakage pass transistors and low supply voltage. The introduction of asynchronous operation in SAPTL further improves energy-delay performance and reliability without increasing hardware complexity. We show two different self-timed approaches using a bundled-data and a dual-rail handshaking protocol, respectively. The proposed self-timed SAPTL architectures provide robust and efficient asynchronous computation using a glitch-free protocol to avoid possible dynamic timing hazards. Simulation results show that the self-timed SAPTL with dual-rail protocol exhibits energy-delay characteristics better than synchronous and bundled-data self-timed approaches.
Asynchronous Circuits and Systems, 2008. ASYNC '08. 14th IEEE International Symposium on; 05/2008
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ABSTRACT: This paper presents a low-power wideband CMOS LNA for low-band UWB application. An NMOS common-gate shunted by a PMOS common-source input stage achieves a wideband impedance matching -7dB from 10MHz to 1.4GHz. RF cascaded by an NMOS common-source output stage sharing the identical input stage bias current 500muA, the 0.18-mum LNA provides a gain 22dB and is insensitive to process variations. The LNA consumes 0.9mW from a 1.8-V supply and occupies an area of 0.03mm<sup>2</sup>
Asian Solid-State Circuits Conference, 2005; 12/2005
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ABSTRACT: This paper presents an implementation of a low-jitter wide-range multi-phase clock generator using a delay-locked loop (DLL) for ultra-wideband (UWB) application. The analog-digital dual-loop adaptive-bandwidth structure, in conjunction with a complementary phase detector (PD), ensures low-jitter clock generation over a wide frequency range. The self-feedback technique reduces the power consumption of the level-shifter circuit 50% at least. The 0.18-μm CMOS prototype exhibits a maximum clock jitter of 3.9 ps (rms) and 28.7 ps (pk-pk) at an output clock rate of 1.6 to 8 GHz (50-250 MHz input reference frequency) and consumes 9.7 mW from a 1.8-V supply at 8 GHz.
Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European; 10/2004
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ABSTRACT: This paper presents the implementation of a low-jitter system clock generator for low-band ultra-wideband (UWB) application based on a wide-range adaptive-bandwidth delay-locked loop (DLL). The false-locking problem commonly along with the wide-range DLL is eliminated by the proposed digital self-correcting loop which also speeds up the lock-in time of the DLL. With self-biased techniques, the proposed DLL adaptively adjusts bandwidth and exhibits optimal jitter transfer characteristic over a wide frequency range and across process, voltage, and temperature (PVT) variations. Fabricated in a 0.18 μm CMOS technology, the design achieves an output multiphase sampling clock rate of 1 to 4 GHz and exhibits the maximum input tracking jitter of 12.06 ps (rms) and 88.9 ps (pk-pk) over the operating frequency range from 31.25 to 125 MHz. The prototype occupies an active area of 360 × 245 μm<sup>2</sup> and consumes 32 mW from a 1.8-V supply at 125 MHz.
Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on; 09/2004
