-
[show abstract]
[hide abstract]
ABSTRACT: This article details an anomalous erase behavior in charge trapping memory devices which is visible in a characteristic erase hump in transient erase curves. For an initial period of time a Vt increase is seen when erase condition are applied to virgin cells before the expected erasing takes place for longer erase pulse duration. This is attributed to charges injected from the gate corners to the areas above source and drain. This effect significantly deteriorates the erase performance of charge trapping devices compared to the intrinsic erase behavior which can be measured at large area capacitor structures.
Non-Volatile Semiconductor Memory Workshop, 2008 and 2008 International Conference on Memory Technology and Design. NVSMW/ICMTD 2008. Joint; 06/2008
-
01/2008;
-
N. Nagel,
T. Muller, M. Isler,
V. Pissors,
J.-U. Sachse,
D. Manger,
D. Caspary,
S. Parascandola,
D. Olligs,
H. Boubekeur, [......],
J. Wilier,
N. Schulze,
C. Ludwig,
E.G. Stein v. Kamienski,
T. Mikolajick,
K.-H. Kusters,
A. Shappir,
Y. Shur,
E. Lusky,
B. Eitan
[show abstract]
[hide abstract]
ABSTRACT: A 63nm Twin Flash memory cell with a size of 0.0225 mum<sup>2</sup> / 2 (4) bits is presented. The cell is proposed for data Flash products with 4 to 16 Gbit densities. To achieve small cell areas, a buried bit line and an aggressive gate length of ~100 nm are the key features of this 63nm Twin Flash cell. The cell is well capable of 2 and 4 bit operation.
VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on; 05/2007
-
M.F. Beug,
R. Knoefler,
C. Ludwig,
R. Hagenbeck,
T. Müller,
S. Riedel, M. Isler,
M. Strassburg,
T. Höhr,
T. Mikolajick,
K.-H. Küsters
[show abstract]
[hide abstract]
ABSTRACT: The extended scalability of Twin Flash memory cells
down to 32.5 nm half pitch is demonstrated in a
conventional planar cell layout. Starting with 65 nm line
space array and doubling the number of word lines, a
cell size of 0.0112 μm² can be achieved. This
corresponds to bit sizes of 0.0056 μm² and 0.0028 μm²
for SLC and MLC mode, respectively. It was found that
the proposed aggressive shrinking of the cell spacing in
word line direction results in a cross talk of 300 mV
when both neighboring cells are programmed to the
highest MLC level. It is reported for the first time that
cross talk in charge trapping memory cells becomes an
issue when the cell spacing approaches the 20 nm mark.
International Conference on Memory Technology and Design (ICMTD), Giens, France; 05/2007
-
Torsten Müller,
C Kleint,
C Fitz, M Isler,
S Riedel,
J -U Sachse,
D Olligs,
H Boubekeur,
F Heinrichsdorf,
V Polei, [......],
L Lattard,
M Markert,
C Schupke,
B Tippelt,
S Teichert,
R Reisdorf,
C Ludwig,
E g Stein v. Kamienski,
T Mikolajick,
N Nagel
[show abstract]
[hide abstract]
ABSTRACT: A 63nm Twin Flash memory cell with a size of 0.0225μm2 per 2 (or 4) bits is presented. To achieve small cell areas, a buried bit line and an aggressive gate length of 100 nm are the key features of this cell together with a minimum thermal budget processing. A novel epitaxial CoSi2 process allows the salicidation of local buried bitlines with only a few tens of nanometer width.
MRS Online Proceedings Library. 01/2007; 997.
-
M F Beug,
R Knoefler,
C Ludwig,
R Hagenbeck,
T Müller,
S Riedel, M Isler,
M Strassburg,
T Höhr,
T Mikolajick,
K -H Küsters
[show abstract]
[hide abstract]
ABSTRACT: The extended scalability of Twin Flash memory cells down to 32.5 nm half pitch is demonstrated in a conventional planar cell layout. Starting with 65 nm line space array and doubling the number of word lines, a cell size of 0.0112 μm² can be achieved. This corresponds to bit sizes of 0.0056 μm² and 0.0028 μm² for SLC and MLC mode, respectively. It was found that the proposed aggressive shrinking of the cell spacing in word line direction results in a cross talk of 300 mV when both neighboring cells are programmed to the highest MLC level. It is reported for the first time that cross talk in charge trapping memory cells becomes an issue when the cell spacing approaches the 20 nm mark.
Proceeding of 2nd ICMTD; 01/2007
-
[show abstract]
[hide abstract]
ABSTRACT: An iterative and time-dependent simulation method based on a full band Monte Carlo algorithm is presented to describe the injection behavior of hot electrons and holes during program and erase of Twin flashtrade memory cells. Secondaries during programming and the feedback of already injected and trapped charge carriers in the ONO nitride on subsequent injection processes are taken into account. By this method it is possible to obtain valuable information on the time-dependent evolution and the local distribution of injection currents and trapped charges in the ONO nitride of the Twin Flashtrade cell
Simulation of Semiconductor Processes and Devices, 2006 International Conference on; 10/2006
-
G. Tempel,
W.V. Emden,
R. Hagenbeck,
P. Haibach, M. Isler,
T. Mikolajick,
T. Muller,
S. Riedel,
J.M. Schley,
J. Schott,
M. Strassburg,
J. Willer
[show abstract]
[hide abstract]
ABSTRACT: Nitride based, localized charge trapping storage flash memory devices with a SONOS stack get increasingly interest due to some advantages compared to conventional floating gate memory devices (Eitan et al., 2000). One of these is the ability to store multi bits in one single cell. There are several previous attempts to simulate and to measure the lateral extend of the localized charges. For the first time, the overall transient programming characteristics is compared with simulations which combine the Monte Carlo (MC) method for the modeling of charge carrier injection and the hydrodynamic (HD) transport model. Distinct features are verified under the assumption of a lateral redistribution of the trapped charges. This model has been proven at all our TwinFlash technologies
Non-Volatile Semiconductor Memory Workshop, 2006. IEEE NVSMW 2006. 21st; 02/2006
-
Non-Volatile Memory Technology Symposium, 2005; 12/2005
-
M Isler,
J -M Schley,
S Riedel,
T Mikolajick,
C Ludwig,
K -H Küsters,
G Tempel,
J -U Sachse,
P Deconinck,
R Mikalo,
R Reichelt,
N Schulze,
E Stein v. Kamienski,
M Strassburg,
J Willer,
F Lau,
R Hagenbeck,
P Haibach
[show abstract]
[hide abstract]
ABSTRACT: The impact of effects due to shallow trench isolation (STI) on the performance of narrow-channel nitride-storage flash memory cells is investigated. By engineering a negative STI step height the gatecontrol is improved, short-channel effects are reduced and the erase speed is significantly increased. One order of magnitude improvement in erase performance is achieved by increasing the hole generation rate by band-to-band tunnelling due to pronounced fringing fields. This translates into an endurance improvement of one order of magnitude and is particularly important for shrinking technology nodes since the erase performance deteriorates as the channel length is downscaled.
Proceeding of 1st International Conference on Memory Technology and Design; 01/2005
-
[show abstract]
[hide abstract]
ABSTRACT: A simulation setup was developed to study the details of electron injection during programming of Twin Flash™ cells. A prerequisite for accurate modeling of injection phenomena caused by high electric fields is the consideration of hot carrier effects. This means that energy transport has to be included in the modeling of charge carrier behavior. This can be done most predictively by solving Boltzmann's transport equation for electrons using the Monte Carlo technique. Alternatively, an energy transport term can be integrated into the classical continuity equation combined with the solution of an additional differential equation for the energy transport. The carrier injection during programming is modeled by the application of a non-local lucky electron model which is based on field line tracing taking into account those electrons having enough energy to overcome the oxide barrier (Meinerzhagen,1988).
Computational Electronics, 2004. IWCE-10 2004. Abstracts. 10th International Workshop on; 11/2004
-
J. Willer,
C. Ludwig,
J. Deppe,
C. Kleint,
S. Riedel,
J.-U. Sachse,
M. Krause,
R. Mikalo,
E.S. Kamienski,
S. Parascandola,
T. Mikolajick,
J.-M. Fischer, M. Isler,
K.-H. Kuesters,
I. Bloom,
A. Shapir,
E. Lusky,
B. Eitan
[show abstract]
[hide abstract]
ABSTRACT: A novel NROM generation with a bit size of 0,043 μm<sup>2</sup>/bit at a 110nm design rule is introduced. The concept features mainstream CMOS type cell devices in conjunction with a metal contact based virtual ground array architecture. The new technology node serves both advanced code flash products and file storage memories up to 2 Gbit/die.
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
-
[show abstract]
[hide abstract]
ABSTRACT: We present a simulation analysis of the transient evolution of the hot electron injection process during programming of a Twin FlashTM memory cell. The simulation model is based on the combination of a non-local lucky electron injection model and a hydrodynamic transport model. The time dependent local distribution of injected electrons is simulated iteratively and self-consistently. These results provide valuable physical insight in the Twin FlashTM programming operation.
Journal of Computational Electronics 01/2004; 3(3):239-242. · 1.21 Impact Factor
-
T Mikolajick,
S Decker,
J -M Fischer,
R Haberkern,
R Hagenbeck,
P Haibach, M Isler,
F Lau,
Ludwig,
S Riedel,
M Straßburg,
G Tempel,
J Willer
[show abstract]
[hide abstract]
ABSTRACT: In recent years multi bit charge trapping cells [1] have received considerable interest due to their very small area per bit, good scalability, simple processing and the absence of single bit errors. Consequently the number of products using this concept, and the number of publications on the subject, have drastically increased in the last 3 years. The physics that govern the operation as well as the reliability of such a cell, was recently studied in detail [2,3,4]. The possibility to simulate programmed and erased cells and the programming and erasing itself, could help to significantly speed up the development time for future scaled down generations.
Proceedings of Nonvolatile Semiconductor Memory Workshop; 01/2004
