[Show abstract][Hide abstract] ABSTRACT: ......Modern embedded, server, graphics, and network processors already include tens to hundreds of cores on a single die, and this number will continue to increase over the next decade. Corresponding increases in main memory bandwidth are also required, however, if the greater core count is to result in improved application performance. Projected enhancements of existing electrical DRAM interfaces are not expected to supply sufficient bandwidth with reasonable power consumption and packaging cost. To meet this many-core memory bandwidth challenge, we are combining monolithic CMOS silicon photonics
[Show abstract][Hide abstract] ABSTRACT: Accurate conversion of wideband multi-GHz analog signals into the digital domain has long been a target of analog-to-digital converter (ADC) developers, driven by applications in radar systems, software radio, medical imaging, and communication systems. Aperture jitter has been a major bottleneck on the way towards higher speeds and better accuracy. Photonic ADCs, which perform sampling using ultra-stable optical pulse trains generated by mode-locked lasers, have been investigated for many years as a promising approach to overcome the jitter problem and bring ADC performance to new levels. This work demonstrates that the photonic approach can deliver on its promise by digitizing a 41 GHz signal with 7.0 effective bits using a photonic ADC built from discrete components. This accuracy corresponds to a timing jitter of 15 fs - a 4-5 times improvement over the performance of the best electronic ADCs which exist today. On the way towards an integrated photonic ADC, a silicon photonic chip with core photonic components was fabricated and used to digitize a 10 GHz signal with 3.5 effective bits. In these experiments, two wavelength channels were implemented, providing the overall sampling rate of 2.1 GSa/s. To show that photonic ADCs with larger channel counts are possible, a dual 20-channel silicon filter bank has been demonstrated.
[Show abstract][Hide abstract] ABSTRACT: The fabrication of complex three-dimensional (3D) structures at sub-100 nm resolution presents a difficult challenge. 3D photonic crystals that contain waveguides, resonant cavities, filters or other devices, and require deep-sub-100 nm dimensional control, are a particular example of this challenge. Multilayer 3D structures can be formed by stacking and bonding thin membranes that have been patterned in advance. This approach enables the full panoply of 2D planar-fabrication techniques to be employed. Membranes containing patterns that are not perfectly regular will exhibit in-plane distortion unless their intrinsic stress is zero. To minimize the effects of intrinsic stress we float individual membranes on the surface of a liquid. Thin single-crystal Si membranes on an oxide substrate are first patterned and then removed by etching the oxide in hydrofluoric acid. The freed Si membranes readily float on the liquid surface, aided by the hydrophobic nature of H-terminated Si. The authors describe methods for cleaning, patterning, manipulating, bonding and stacking such freely floating membranes.
Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures 11/2011; 29(6). DOI:10.1116/1.3628672 · 1.36 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: The authors describe an approach to fabricating high resolution, complex 3D structures based on the stacking of thin membranes that have been patterned in advance. The membranes are attached to a rigid frame by means of tethers that are strong enough to permit normal handling but can be cleaved after bonding. The tether shape was designed using finite-element analysis to enable clean cleavage at a specific location so that fragments are avoided that would interfere with the bonding of subsequent layers. The authors used 12 × 12 mm SiNx membranes, 350 nm thick, patterned with a square array of holes at 600 nm pitch and demonstrate the stacking of three layers.
Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures 11/2011; 29(6). DOI:10.1116/1.3643762 · 1.36 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: The secondary-electron signal levels of eight thiophenol-based self-assembled monolayers (SAMs) on gold (Au) are measured and compared against the signal level from bare gold between energies 1 and 2 keV. To enable accurate comparison, scanning electron micrographs of SAMs are taken with a Faraday cup and a reference sample. Most SAMs-on-gold produce a lower signal level than that from bare gold, with the exception of 3-methylthiophenol. Highest occupied molecular orbital and lowest unoccupied molecular orbital levels of the thiophenol derivatives are calculated and compared against the signal levels. Signal levels from bis[3-(triethoxysilyl)propyl]tetrasulfide, (4-chlorophenyl)-triethoxysilane, and amino-propyl-triethoxy-silane on titanium (Ti) and aluminum (Al) are also measured. All three SAMs on aluminum have lower signal levels than bare Al but this effect is reversed for the case of Ti, where SAMs deposited on Ti result in a higher signal level. A hybrid Ti/Al fiducial grid is fabricated and the point-spread function at 2 keV in the underlying resist is investigated.
Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures 11/2011; 29(6). DOI:10.1116/1.3646897 · 1.36 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: We fabricated 9–30 nm half-pitch nested Ls and 13–15 nm half-pitch dot arrays, using 2 keV electron-beam lithography with hydrogen silsesquioxane (HSQ) as the resist. All structures with 15 nm half-pitch and above were fully resolved. We observed that the 9 and 10-nm half-pitch nested Ls and the 13-nm-half-pitch dot array contained some resist residues. We obtained good agreement between experimental and Monte-Carlo-simulated point-spread functions at energies of 1.5, 2, and 3 keV. The long-range proximity effect was minimal, as indicated by simulated and patterned 30 nm holes in negative-tone resist.
[Show abstract][Hide abstract] ABSTRACT: We demonstrate a monolithic photonic integration platform that leverages the existing state-of-the-art CMOS foundry infrastructure. In our approach, proven XeF2 post-processing technology and compliance with electronic foundry process flows eliminate the need for specialized substrates or wafer bonding. This approach enables intimate integration of large numbers of nanophotonic devices alongside high-density, high-performance transistors at low initial and incremental cost. We demonstrate this platform by presenting grating-coupled, microring-resonator filter banks fabricated in an unmodified 28 nm bulk-CMOS process by sharing a mask set with standard electronic projects. The lithographic fidelity of this process enables the high-throughput fabrication of second-order, wavelength-division-multiplexing (WDM) filter banks that achieve low insertion loss without post-fabrication trimming.
[Show abstract][Hide abstract] ABSTRACT: We report the fabrication of a reconfigurable wide-band twenty-channel second-order dual filterbank, defined on a silicon-on-insulator (SOI) platform, with tunable channel spacing and 20 GHz single-channel bandwidth. We demonstrate the precise tuning of eleven (out of the twenty) channels, with a channel spacing of 124 GHz (~1 nm) and crosstalk between channels of about -45 dB. The effective thermo-optic tuning efficiency is about 27 μW/GHz/ring. A single channel of a twenty-channel counter-propagating filterbank is also demonstrated, showing that both propagating modes exhibit identical filter responses. Considerations about thermal crosstalk are also presented. These filterbanks are suitable for on-chip wavelength-division-multiplexing applications, and have the largest-to-date reported number of channels built on an SOI platform.
[Show abstract][Hide abstract] ABSTRACT: Ion beam enhanced grain growth has been investigated in thin films of Ge. Grain boundary mobilities are greatly enhanced over their thermal equilibrium values and exhibit a very weak temperature dependence. We propose that defects which are generated by the ion beam at or near the grain boundary are responsible for the boundary mobility enhancement. Films of Ge deposited under different conditions, either unsupported or on thermally oxidized Si, exhibit similar normal grain growth enhancement when implanted with 50 keV Ge** plus . Beam-enhanced grain growth in Ge was also demonstrated using Xe** plus , Kr** plus , and Ar** plus ions. The variation in growth enhancement with projectile ion mass is in good agreement with the enhanced Frenkel defect population calculated using a modified Kinchin-Pease formula and Monte Carlo simulation of ion transport in thin films.
[Show abstract][Hide abstract] ABSTRACT: Two approaches to preparing oriented crystalline films on amorphous substrates are reviewed briefly: zone-melting recrystallization (ZMR) and surface-energy-driven grain growth (SEDGG). In both approaches patterning can be employed either to establish orientation or to control the location of defects. ZMR has been highly successful for the growth of Si films on oxidized Si substrates, but its applicability is limited by the high temperatures required. SEDGG has been investigated as a potentially universal, low temperature approach. It has been demonstrated in Si, Ge, and Au. Surface gratings favor the growth of grains with a specific in-plane orientation. In order for SEDGG to be of broad practical value, the mobility of semiconductor grain boundaries must be increased substantially. Mobility enhancement has been achieved via doping and ion bombardment.
[Show abstract][Hide abstract] ABSTRACT: Ion bombardment of polycrystalline Ge, Si, and Au films leads to rates of grain boundary motion that greatly exceed rates of thermally-induced motion at the same temperature and which exhibit a weak temperature dependence. The enhanced migration rate is proportional to the rate of energy deposition in nuclear collisions at or very near the grain boundary. Experimental work is reviewed, and a transition state model is presented which accounts for the observed kinetics of grain boundary migration during bombardment. This model suggests that the rate limiting step in grain boundary motion may be thermally-induced migration of a bombardment-generated defect across the boundary. Also, the ratio of atomic jumps at grain boundaries to the local collision-induced Frenkel defect generation rate is shown to be characteristic of each material, but independent of ion mass and ion flux. The model is extended to the motion of an interface between two phases, and applications to crystallization during ion bombardment are discussed.
[Show abstract][Hide abstract] ABSTRACT: In-plane magnetic anisotropy can be induced in Cr-underlayer/Co-alloy thin films by grooves or scratches in the substrate. To quantify this effect, silica substrates have been prepared with large areas of submicron grooves using interferometric lithography. The growth of Cr films and Cr/Co-alloy bilayer films on these substrates has been investigated, and in-plane magnetic anisotropy has been observed.
[Show abstract][Hide abstract] ABSTRACT: Subboundaries are the major crystalline defects in thin semiconductor films produced by zone-melting recrystallization (ZMR). Using transmission electron microscopy (TEM) and chemical etching, the authors analyzed the angular discontinuity and defect structure of subboundaries. Annealing in oxygen resulted in elimination of dislocation bands from some films. Calculations suggest that cellular growth due to constitutional supercooling may not occur in some Si ZMR.
[Show abstract][Hide abstract] ABSTRACT: A novel dynamical slow light cell with a tunable group delay, fabricated in silicon-on-insulator, is demonstrated. It provides a tuning range of more than 1 ns, with a usable group delay of about 0-24 ps.