[show abstract][hide abstract] ABSTRACT: Supercapacitor aging is mainly related to thermal and voltage constraints. This aging causes degradation in the supercapacitor performances which can lead to the failure of this component. To avoid this failure, it is necessary to determine the supercapacitor state of health. The aim of this study is the supercapacitor diagnosis. In this paper, aging tests of supercapacitor subjected to calendar aging constraints are presented. The supercapacitor is aged at constant temperature and constant bias voltage. During the aging process, the variations of the supercapacitor equivalent series resistance (ESR) and equivalent capacitance (C) are measured and analyzed. For diagnosis, a least square algorithm is used. This algorithm is used for ESR and C identification during the supercapacitor operation. For vehicle applications, the supercapacitor is considered as aged when the capacitance loss is in order of 20% of its initial value, or if the value of the equivalent series resistance increases by a factor of 2.
[show abstract][hide abstract] ABSTRACT: In this paper, a new nonlinear control strategy for static boost type converters is proposed. This control law is an extension of the high gain control algorithm which takes into account the input model parameter uncertainties. Unlike traditional high gain approaches, the integral action is directly incorporated into the physical variables basis. This ensures constant performances even in presence of parametric uncertainties. In addition, the present control algorithm doesn't need the measurement of the battery voltage and the current load. These variables are estimated online with a nonlinear observer. The algorithm presented here is validated on a dedicated electric vehicle converter and experimental results are provided.
[show abstract][hide abstract] ABSTRACT: This paper deals with the effects of 60Co gamma irradiation on punch-through commercial insulated gate bipolar transistor turn-on switching behaviour. The response of the threshold voltage and the turn-on switching parameters under three different in situ gate biases are described. Charge trapping in the gate oxide causes the decrease of the threshold voltage. It is shown that the decrease of this parameter and the decrease of the Miller plateau level result in a decrease of the collector current rise-time, the collector–emitter voltage fall-time, the turn-on switching energy and in an increase of the peak of the turn-on switching instantaneous power and of the turn-on overshoot collector current.
[show abstract][hide abstract] ABSTRACT: The ageing of power insulated gate bipolar transistor (IGBT) modules is mainly related to thermal and thermomechanical constraints applied to the device. This ageing causes degradation of the device performances and defects appearance which can lead to failures. To avoid these failures, the follow-up of the device operation and the detection of an ageing state remain a priority. This paper presents, at first, ageing tests of 1200V–30A IGBT module subjected to power cycling with the aim to highlight online and real-time measurable external indicators of ageing. Secondly, these indicators are used to develop a failure diagnosis method. The diagnosis is realized by artificial training methods based on pattern recognition.
[show abstract][hide abstract] ABSTRACT: The success of the high temperature power electronic applications depends on the power device reliability. The increasing thermal demands, like in hybrid electric cars, require power devices operating at junction temperatures above their common level of 125 °C. The thermal cycles generated in standard modules in such conditions induce several failure mechanisms in their package and chips. This article presents ageing tests of an EconoPIM IGBT module submitted to PWM power cycling at high ambient temperature. Several electrical and thermal parameters are monitored to detect failure onsets in the module components. Static and dynamic measurements are periodically made to reveal possible module characteristic drifts, and to better understand the effects of this kind of cycling test on the module static and switching behaviors. The follow-up of the dynamic parameter evolution represents the originality of this study.
[show abstract][hide abstract] ABSTRACT: This paper presents supercapacitor ageing according to the voltage, the temperature and thermal shock tests. To investigate this effect, a test bench of accelerated supercapacitor calendar ageing was carried out. Experimental tests are realized at constant temperature when the supercapacitors are polarized at the maximum voltage. To quantify the supercapacitor ageing, the equivalent series resistance (ESR) and the equivalent capacitance (C) are measured using the DC and AC characterization. To lead to the determination of the supercapacitor lifetime, Arrhenius law, that describes the effect of temperature on the velocity of a chemical reaction, is considered. Finally, experimental results of supercapacitor thermal shock are presented.
[show abstract][hide abstract] ABSTRACT: The work presented in this paper is concerned with the effects of a positive and of a negative gate bias stress on punch-through insulated gate bipolar transistors (PT-IGBT's). Two selections of PT IGBT's all of the same nominal range were gate biased at their positive and negative maximum gate-to-emitter voltage with drain and emitter short-circuited at 140 °C during 1200 hours. A particular interest was taken in the switching parameters. Experimental results on their evolution under the two types of stress are presented in a quantified way. Then, a qualitative analysis of the effects of the switching times shift, due to the IGBT's ageing, on a PWM inverter operation is presented.
Industrial Electronics, 2005. ISIE 2005. Proceedings of the IEEE International Symposium on; 07/2005
[show abstract][hide abstract] ABSTRACT: The work presented in this paper is concerned with the effects of a high temperature gate bias (HTGB) and a high temperature reverse bias (HTRB) stresses on non-punch-through IGBTs. The stresses were achieved during 1200 hours at 140degC. A particular interest was taken in the parameters related to the switching mode operation and experimental results on their evolution under the two types of stress are presented in a quantified way. A qualitative analysis of the switching times effects, due to the IGBTs ageing, on a pulse width modulation (PWM) inverter operation is presented
[show abstract][hide abstract] ABSTRACT: In this work we analyse the behavior of the Non Punch Through Trench Insulated Gate Bipolar Transistors submitted to High Temperature Gate Bias (HTGB) and High Temperature Reverse Bias (HTRB) stresses. The electric stress has been accomplished during 1200 hours at 140 °C with 0.8 VCEmax Collector - Emitter bias (HTRB) and with VGE = −20 V or +20 V Gate Bias (HTGB). The results show the evolution of the static parameters as threshold voltage and on-state voltage drop and of switching parameters. The aim is to constitute a database as complete as possible for the analysis and diagnosis of failure causes related to the switching devices in power conversion systems.
[show abstract][hide abstract] ABSTRACT: The work presented in this paper is concerned with the effects of a high temperature gate bias (HTGB) stress on punch-through (PT) and non-punch-through (NPT) insulated gate bipolar transistors (IGBTs). A selection of PT IGBTs and a selection of NPT IGBTs all of the same nominal range were gate biased at their maximum gate-to-emitter voltage with drain and emitter short circuited at 140 °C during 1200 hours. A particular interest was taken in the switching parameters. The turn-on delay time t<sub>don</sub> increases for the PT IGBTs while it decreases for the NPT IGBTs. The switching losses and the rise time increase for the two technologies. The turn-off delay time monotonically decreases for both the PT and NPT IGBTs. The fall time decreases for the PT IGBTs whereas it increases but in a less important way for the other technology. The on state voltage drop increases in both cases and in a more important way for the PT IGBTs. The gale threshold voltage is quiet insensitive to this type of stress for the NPT IGBTs whereas it increases during the first hundred hours of stress and remains unchanged thereafter for the PT IGBTs. The gate leakage current increases strongly for the two technologies while the collector leakage current, such as the threshold voltage, increases to remain constant after some hours of stress for the PT IGBTs.
Industrial Electronics, 2004 IEEE International Symposium on; 06/2004
[show abstract][hide abstract] ABSTRACT: Previous works on the study of the state creation under gate-bias stress in polysilicon thin film transistors (TFTs) are extended here by some measurements of the transfer characteristics in the temperature range from 90 to 400 K. Using two different qualities of the active layer polysilicon material, the analysis gives evidence of this state creation. Moreover, and surprisingly, the measurements show a nearly constant on-current at temperature lower than 300 K. So, the field effect mobility is nearly constant from 300 to 90 K and, due to the decrease of the off-current, the Ion/Ioff ratio increases from 107 at 300 K to 109 at 90 K. The density of states (DOS) is calculated assuming polycrystalline silicon as a spatially homogeneous material with a uniform distribution of the DOS in the bulk. Using the transconductance of the TFTs at different temperatures, we can check a wide region of the band-gap. The calculation gives a nearly constant DOS in a large part of the gap and very low extended band-tails. A bump, more important with the lower quality material, appears in the DOS after negative gate bias stress.
Thin Solid Films 01/2003; 427(1):340-344. · 1.60 Impact Factor
[show abstract][hide abstract] ABSTRACT: The stability of polycrystalline structure is studied by means of the behavior of thin film transistors (TFTs) under gate bias stress with shortened drain and source contacts. Gate bias stress affects the parameters of all TFTs. Experiments show that the stability depends on the importance of the disordered regions that are the grain boundaries, as well as on the behavior of impurities. The behavior of the threshold voltage during the gate bias stress obeys the stretched exponential law exp(t/t0)β. This law, usually encountered in a great variety of situations such as a-Si:H TFTs, single crystal silicon MOSFET and even glasses, is linked to the disordered structure independent of the presence of hydrogen. The structure is less stable when impurities such as hydrogen, oxygen and others, are present.
Journal of Non-Crystalline Solids 01/2002; · 1.60 Impact Factor
[show abstract][hide abstract] ABSTRACT: The performance of polysilicon thin film transistors used in large-area electronics applications, directly depends on the structural quality of the channel material. Moreover, their stability under electrical stress is shown, in this work, to also depend on the quality of the channel material. TFTs were fabricated using several channel materials, deposited as an amorphous film by low-pressure chemical vapor deposition (LPCVD), and then crystallized using solid-phase annealing, a large-area pulsed excimer laser, or scanning with a 532-nm beam of a pulsed diode pumped Nd:YVO4 laser. The stability of the TFTs, determined from the increase in the subthreshold slope S, is shown to be related to the importance of the surface roughness and to the structural quality of the crystallized active layer. With similar surface roughness, the stability is better when the structural quality of the active layer is improved. The increase in S is then explained by the creation of a state in the channel material that is more effective when the structure of the polysilicon is more disordered.
Thin Solid Films 01/2001; 383(1):299-302. · 1.60 Impact Factor
[show abstract][hide abstract] ABSTRACT: Ageing of low temperature polysilicon Thin Film Transistors (TFTs) under AC gate bias stress is reported in this study. The active layer of these high performances transistors is amorphous deposited using Low Pressure Chemical Vapor Deposition (LPCVD) technique. The drain and source regions are in-situ doped during the LPCVD deposition by using phosphine to fabricate n-type transistors. The active layer and the drain arid source regions are Solid Phase Crystallized. The field effect mobility is higher than 100 cm2/V.s, the subthreshold slope around 0.6 V/dec, the threshold voltage around 0.2V and the switching time around 370 nsec.As these TFTs are commonly used as switching devices in the most of applications in large area electronics field, the study of their stability under AC electrical stress is important. The present work shows that the effect of the positive or negative DC stress is higher than that of the AC stress and then the degradation of polysilicon TFTs is over-estimated when it is checked from the effects of DC gate bias stress.Degradation under bias stress is shown to originate from the creation of gap states at the channel-interface oxide and in the channel material. The lower influence of the AC stress is explained from an annealing effect of the created states by the application of an opposite sign bias stress.