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ABSTRACT: Here is a complete methodology of substrate noise modeling. The aim of this study is to predict the perturbations induced by digital commutations flowing through the substrate to reach sensitive analog blocks. Till now, the studies have only taking into account the parasitic elements of the bonding wires. This work consists of each part of a mixed-signal design that induces power-and-ground bounces: the printed circuit board, the package, the bonding wires, the input-output ring, the on-chip power-supply distribution, and the digital core of the chip. A standard approach, called integrated circuit (IC) emission model, is used to create the substrate simulation model. By adding some elements to this power-supply model, we can simulate the transient substrate voltage induced by the digital part of a mixed-signal IC. A test chip has been realized in a 0.35-mum BiCMOS process to validate this substrate coupling model. Power-supply network, chip activity and substrate propagation of this circuit are obtained by using classical computer-aided design tools. Some Spice simulations of the modeled test chip, running in many different configurations, are shown. Comparisons between measurements and simulations are done and lead to the conception of an optimized version of the same circuit that induces less parasitic substrate voltages
Circuits and Systems I: Regular Papers, IEEE Transactions on 11/2006; · 1.97 Impact Factor
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ABSTRACT: This work investigates substrate coupling effects in mixed IC's, especially the perturbations on RF block. The authors present the impact of low frequency substrate noise perturbations on voltage-controlled oscillator (VCO) spectrum. A 5 GHz VCO test-chip is presented; several substrate taps have been placed inside VCO core to measure or to inject noise perturbations. The oscillation frequency sensitivity function of tuning voltage or bias current and spurious side-bands due to injected noise are measured to find out a relation between substrate noise and spectrum purity. Finally, a significant link between such device sensitivity functions and VCO spurs magnitude is demonstrated.
Microelectronics, 2004. ICM 2004 Proceedings. The 16th International Conference on; 01/2005
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ABSTRACT: An alternative way of using the ICEM model is described. This model is considering each part of a mixed signal design: the PCB, the package, the bonding wires, the padring and the core of the digital chip. By adding some elements to this model, we can simulate the transient substrate voltage induced by the digital part of a mixed signals integrated circuit. A test-chip was implemented in a 0.35 μm BiCMOS process to validate this extended ICEM model. Some spice simulations of the modelled test-chip, running in many different configurations, are exposed. The results of those simulations are compared to measurements and reveal the advantages and drawbacks points of the methodology. We also describe what has to be done to apply this method to a realistic digital circuit.
Microelectronics, 2004. ICM 2004 Proceedings. The 16th International Conference on; 01/2005
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ABSTRACT: Digital signal slope incidences on coupling mechanisms and noise generation in mixed-signal integrated circuits are developed and illustrated by some SPICE simulations. The minimum transition concept on some signals should allow us to reduce the noise generated by the digital part of a system on chip. Some noise measurements on silicon, caused by single inverters, confirm that reducing the slope of digital edge can decrease significantly the perturbing crosstalk in a mixed analog-digital integrated circuit. A digital design method is exposed and used to create a small block, which has the typical behaviour of used existing IPs. Comparative SPICE simulations, between a classical implemented block and a special one with well-fitted transitions, show that a noise reduction is easily obtained by increasing several transition times of digital signals without decreasing the device speed. For larger circuit, a step called 'recovery', would be included in the design implementation flow, in order to decrease some too fast transitions.
Industrial Electronics, 2004 IEEE International Symposium on; 06/2004
