[Show abstract][Hide abstract] ABSTRACT: We describe, in this paper, a new digital input-output power configurable PAD (CPAD) for a wafer-scale-based rapid prototyping platform for electronic systems. This wafer-scale platform includes a reconfigurable wafer-scale circuit that can interconnect any digital components manually deposited on its active alignment-insensitive surface. The whole platform is powered using a massive grid of embedded voltage regulators. Power is fed from the bottom side of the wafer using through silicon vias. The CPAD can be configured to provide CMOS standard voltages of 1.0, 1.5, 1.8, 2.0, 2.5, and 3.3 V using a single 3.3 V power supply. The digital I/O includes transistors sharing and is embedded within the regulation circuit by combining it with a turbo mode that insures high-speed operation. Fast load regulation is achieved with a 5.5-ns response time to a current step load for a maximum current of 110 mA per CPAD. The proposed circuit architecture benefits from a hierarchical arborescence topology where one master stage drives 16 CPADs with a very small quiescent current of 366 nA. The CPAD circuit and the master stage occupy a small area of 0.00847 and 0.00726 mm2, respectively, in CMOS 0.18-μm technology.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 01/2013; 21(11):2024-2033. · 1.22 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: This paper introduces the power supply analysis of a large area integrated circuit (LAIC) used in a rapid prototyping platform for electronic systems. User integrated circuits deposited on this active LAIC surface receive power through configurable IOs. Strategies to distribute power all over a LAIC of the size of an entire wafer are described, modeled and their performances evaluated. Different scenarios have been investigated considering technological and physical constraints. A strategy has been implemented in a mature and low-cost 7-metal layers CMOS 0.18 μm technology. It uses advanced Through Silicon Vias (TSVs) to support up to 1000 W of power consumption. Detailed power analysis is provided. It is based on a finite element model (FEM) of the power grid. The FEM simulations allow determining the power density flowing through TSVs, as well as that flowing in the metal stripes which allow sizing these components in a way that meets electromigration and IR drop design constraints.
New Circuits and Systems Conference (NEWCAS), 2011 IEEE 9th International; 07/2011
[Show abstract][Hide abstract] ABSTRACT: In new circuits performed with 3D integration technology, electromagnetic interference through stacked silicon substrates may occur due to signals propagated in Through Silicon Vias (TSV) and along Redistribution Layers (RDL). So, to optimize electrical performances of these new 3D digital or RF circuits, substrate coupling effects need to be characterized, modeled and quantified in a large frequency bandwidth. In this paper, we mainly analyze substrate coupling effects using dedicated capacitive test structures These structures are characterized using aggressive RF or high speed signals propagated along Through Silicon Vias (TSV). These RF or time domain signals in TSV are used to generate parasitic noise signals in silicon substrates. By analyzing the extracted results, solutions will be proposed to reduce this substrate noise.
[Show abstract][Hide abstract] ABSTRACT: This work addresses parasitic substrate coupling effects in 3D integrated circuits due to Through Silicon Vias (TSV). Electrical characterizations have been performed on dedicated test structures in order to extract electrical models of substrate coupling phenomena when RF signals are propagated in TSV. A good compatibility between RF measurements and RF simulations allows validating modeling tools for predictive studies. Next, parametric studies are performed in order to study impact of TSV design and materials on substrate coupling noise.
[Show abstract][Hide abstract] ABSTRACT: This paper is essentially composed of two parts for future synthesis. We developed 2D and 3D simulations, starting from a 0.35μm standard CMOS technology, focusing on through silicon via or redistribution layer induced coupling; nMOSFET, pMOSFET, and the sensitive regions of the CMOS inverter are investigated. We also study stacked devices in 3D circuits, in the radiofrequency range, and propagation of electromagnetic waves along some interconnections with discontinuities. This study is performed in the time domain—a finite-difference time-domain method is applied to the analysis of some vias flanked by two striplines, all embedded in silicon. Electric and magnetic field distributions, transmission and reflexion parameters, and pulse propagations along a transverse via are presented.
[Show abstract][Hide abstract] ABSTRACT: A programmable voltage reference used in an advanced wafer-scale hierarchical voltage regulation circuit is presented. The novel arborescence structure of the voltage regulation system is described and the requirements for the voltage reference derived. The proposed programmable voltage reference is based on beta-multiplier architecture, implemented in 0.18 μm CMOS technology with a very small area of 0.0014 mm<sup>2</sup>. It provides several output voltage references between 1.0 and 2.5 V from an input voltage between 3.0 and 4 V. The overall divergence is less than 10 % from desired output levels, which makes the use of a complete bandgap non-essential for our application. We gave priority to fit in the small allowed area with limited power consumption. The total power consumption of the whole voltage reference module is 386 μW and its static power consumption drops to 0.66 nW when turned off.
[Show abstract][Hide abstract] ABSTRACT: This paper discusses substrate coupling effects in 3D integrated circuits carried by TSV interconnects (Through Silicon Vias). These electrical couplings lead to several impacts on 3D circuit performance. RF (Radio Frequency) characterizations have been performed on dedicated test structures in order to extract electrical models of substrate coupling and make obvious this phenomenon. New modeling tools for predictive studies have been validated thanks to a good compatibility between RF measurements and RF models.
Signal Propagation on Interconnects (SPI), 2010 IEEE 14th Workshop on; 06/2010
[Show abstract][Hide abstract] ABSTRACT: Predicting substrate cross-talks in mixed-signal circuits has become a critical issue to preserve signal integrity in future
integrated systems. Phenomena that involve substrate parasitic voltage and substrate propagation are discussed. A simple methodology
to predict the substrate cross-talk and some associated tools are presented. A typical study shows the possibility of such
a method and measurements finally demonstrate its efficiency.
KeywordsIntegrated circuit noise-Mixed analog-digital integrated circuits-Substrate noise-Design methodology-VCO
Analog Integrated Circuits and Signal Processing 05/2010; 63(2):185-196. · 0.55 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: This paper presents an interface that is spatially programmable and that was designed to support fast differential signaling on a novel reconfigurable CMOS wafer-scale platform for electronic system prototyping. The device called WaferIC has a sea of tiny openings on its surface to adapt to the contact type, size, spacing and alignment of external integrated circuit components. The physical and electrical constraints of the needed wafer-scale differential configurable system are described, and an architecture is proposed for transmitting Current Mode Logic (CML) differential signals between two different integrated circuits deposited on the WaferIC surface. A small piece of the wafer scale active substrate has been implemented into a test-chip using a mature 0.18 μm CMOS technology. Post layout simulations show that under normal conditions, the configurable differential link can operate up to 2.5 Gbps.
17th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, Athens, Greece, 12-15 December, 2010; 01/2010
[Show abstract][Hide abstract] ABSTRACT: This paper presents an interconnection network embedded in a novel reconfigurable circuit board for rapid electronic system prototyping. This system supports high pincount packages and high density system integration requirements. It can be configured to interconnect integrated circuits and other components at near-intra-chip density. This is achieved using a fault-tolerant interconnection network called WaferNet™, supported by a repeated cell-pattern in a large integrated circuit that can scale up to a full wafer. The design has been manufactured on a 1/10,000<sup>th</sup> of a full 200 mm wafer, by using a standard 0.18µm CMOS technology. Measurements on the test chip on a custom test board validate the defect tolerant interconnection network for different propagation paths and show that it can propagate digital signals at 270 Mbps@3.3V between two different circuit pins with loads of 5pf, as predicted by simulations.
Microsystems and Nanoelectronics Research Conference, 2009. MNRC 2009. 2nd; 11/2009
[Show abstract][Hide abstract] ABSTRACT: This paper investigates the signal integrity and performance of a novel programmable interconnect technology called DreamWafertrade. This programmable circuit board uses a wafer-scale circuit with a sea of tiny contacts to adapt to the contact type, size, spacing and alignment of external components. Supporting this ability to adapt requires a dense internal programmable interconnect network to propagate digital signals between arbitrary sets of contacts. The means to propagate the digital signals are described and characterized. Propagation delays of the chain as well as its rise and fall time characteristics are simulated. Preliminary results show that under normal conditions, the links can operate up to 630 MHz and have a mean latency of 0.3 ns/mm. Eye diagrams demonstrate improvements in the signal integrity when a signal is propagated on the DreamWafertrade interconnect compared to when it is propagated on a traditional PCB trace; the eye remains open and neat, independently of the linkpsilas length.
Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on; 10/2008
[Show abstract][Hide abstract] ABSTRACT: This paper introduces an innovative reconfigurable circuit board for rapid system prototyping. This system supports high pin-count packages and high density system integration requirements, and can be programmed to interconnect integrated circuits and other components at near-intra-chip density. This paper presents the concept and investigates several aspects related to its feasibility. Considered factors include technological and physical constraints; architectural and system aspects; design and technology considerations. Preliminary results are promising, confirming that this smart reconfigurable circuit board can be implemented using a wafer-scale approach in a mature and low-cost 6-metal layer CMOS 0.18 mum technology, with the associated classical design CAD tools and flow. The achieved contact density is sufficient to interconnect components packaged with todaypsilas peripheral I/O and fine-pitched BGA packages.
Circuits and Systems and TAISA Conference, 2008. NEWCAS-TAISA 2008. 2008 Joint 6th International IEEE Northeast Workshop on; 07/2008
[Show abstract][Hide abstract] ABSTRACT: This paper presents a programmable interconnection network for a novel multi-reticle integrated circuit providing a reconfigurable circuit board for rapid system prototyping. This multi-dimensional mesh grid network, called WaferNettrade, can actively interconnect any pair of pins of integrated circuits deposited on the configurable system board. Two crossbar architectures are implemented and compared, one based on crosspoints and one based on standard cell multiplexers. Implementation results show the feasibility of this proposed cell-based array network that could interconnect a very large number of nodes, spread over an area that could fill a whole wafer, using a typical 6-metal 0.18 mum CMOS technology.
Circuits and Systems and TAISA Conference, 2008. NEWCAS-TAISA 2008. 2008 Joint 6th International IEEE Northeast Workshop on; 07/2008
[Show abstract][Hide abstract] ABSTRACT: Investigations on the electromagnetic behaviour of a low-power amplifier are led using the extended-integrated circuit emission model (ICEM). This modeling approach is proposed on a mixed-signal (analog/digital) CMOS 0.18 mum circuit dedicated to neural signal recording. This ICEM allows coarse and fast studies of the electromagnetic compatibility of CMOS devices especially in characterizing the coupling phenomena that occurs at each building block inside the whole chip. ICEM simulations of power and ground bounces are more than 500 times faster than complete SPICE ones with a correct accuracy for first electromagnetic compatibility investigations. This quick modeling method allows for checking many different design or simulation configurations. For example, some simulation results show that substrate interactions and power/ground crosstalk increase the noise level of the low-noise amplifier, in particular in its low frequency domain.
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on; 06/2007
[Show abstract][Hide abstract] ABSTRACT: The purpose of this paper is to investigate the significance of different coupling mechanisms that occur in a high precision D/A converter. The standard Integrated Circuit Emission Model approach is applied to an existing D/A converter built in TSMC CMOS 0.25 Â¿m technology. Aggressors, propagation media and victims are defined and modelled using classical CAD tools. Potential noise sources and victims are identified and some frequency and time domain simulation results reveal the noise source signatures. This study highlights the main noise source in such kind of converters: the charging/ischarging switch current that occur at each sampling period. Based on detailed simulations, the 60mV peak to peak voltage glitch observed on the output is explained by power and ground ringing due to current switches, whereas previous studies suggested that such glitches were due to substrate coupling. The simulated substrate propagated digital glitches have a peak to peak voltage of 5mV, and are more than ten times lower than glitches induced by the current switch activities.
Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on; 01/2007
[Show abstract][Hide abstract] ABSTRACT: Here is a complete methodology of substrate noise modeling. The aim of this study is to predict the perturbations induced by digital commutations flowing through the substrate to reach sensitive analog blocks. Till now, the studies have only taking into account the parasitic elements of the bonding wires. This work consists of each part of a mixed-signal design that induces power-and-ground bounces: the printed circuit board, the package, the bonding wires, the input-output ring, the on-chip power-supply distribution, and the digital core of the chip. A standard approach, called integrated circuit (IC) emission model, is used to create the substrate simulation model. By adding some elements to this power-supply model, we can simulate the transient substrate voltage induced by the digital part of a mixed-signal IC. A test chip has been realized in a 0.35-mum BiCMOS process to validate this substrate coupling model. Power-supply network, chip activity and substrate propagation of this circuit are obtained by using classical computer-aided design tools. Some Spice simulations of the modeled test chip, running in many different configurations, are shown. Comparisons between measurements and simulations are done and lead to the conception of an optimized version of the same circuit that induces less parasitic substrate voltages
Circuits and Systems I: Regular Papers, IEEE Transactions on 11/2006; · 2.24 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: This paper presents the impact of low-frequency substrate disturbances on a fully integrated voltage-controlled oscillator (VCO) spectrum. A 4.5GHz VCO test-chip is presented; two substrate taps are placed inside the VCO core to measure or to inject disturbances into the substrate. The VCO carrier frequency sensitivity function of the tuning voltage and the bias current are measured. Then, the VCO spurious side-bands caused by harmonic substrate noise disturbances are analyzed to find a relation between the substrate noise characteristics and spur magnitudes. Theoretically the impulse sensitivity function (ISF) approach is used to analyze device sensitivity to substrate noise. Finally, a significant link between device sensitivity functions, low-frequency substrate disturbances and the VCO side-band spectral power, is demonstrated. According to this study, we conclude that a global approach which only considers power supply bounces in mixed IC's is not sufficient to analyze the sensitivity of RF integrated oscillators to low frequency substrate noise.
[Show abstract][Hide abstract] ABSTRACT: This work investigates substrate coupling effects in mixed IC's, especially the perturbations on RF block. The authors present the impact of low frequency substrate noise perturbations on voltage-controlled oscillator (VCO) spectrum. A 5 GHz VCO test-chip is presented; several substrate taps have been placed inside VCO core to measure or to inject noise perturbations. The oscillation frequency sensitivity function of tuning voltage or bias current and spurious side-bands due to injected noise are measured to find out a relation between substrate noise and spectrum purity. Finally, a significant link between such device sensitivity functions and VCO spurs magnitude is demonstrated.
Microelectronics, 2004. ICM 2004 Proceedings. The 16th International Conference on; 01/2005