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ABSTRACT: The mechanism governing threshold voltage (V<sub>t</sub>) modulation in NiSi/SiON n -channel metal-oxide-semiconductor field-effect transistors when doping with rare-earth elements (dysprosium or Dy in this work) is studied. In addition to the widely reported interface dipole theory, this letter provides additional evidence that the bulk trapping charges (related to the unintermixed Dy <sub>2</sub> O <sub>3</sub> layer after device fabrication) can play an important role in determining the device V<sub>t</sub> for the above-mentioned gate stacks. It is thus suggested that a careful design of the capping layer thickness and the thermal budget for intermixing the capping layer with host dielectrics is necessary to eliminate the impact from bulk trapping charges to the device performance.
Applied Physics Letters 01/2009; · 3.84 Impact Factor
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ABSTRACT: This paper provides a comprehensive study on the integration of LaO<sub>x</sub> capping layer for sub-45 nm metal gated CMOS devices with Hf-based high-K dielectrics in a gate first manner. Two different integration routes, i.e. Dual Metal Dual Dielectric flow (DMDD) and Single Metal Dual Dielectric (SMDD) flow, are reported and compared. The device reliability study is also provided.
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on; 11/2008
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ABSTRACT: For the first time, the effect of the poly-Si gate electrode deposition process on the electrical characteristics of Ni-based fully silicided/HfO<sub>2</sub> gate stacks is investigated. The flat- band voltage V<sub>fb</sub> of Ni<sub>2</sub>Si/HfO<sub>2</sub> (or Ni<sub>3</sub>Si/HfO<sub>2</sub>) with a physical vapor deposited (PVD) Si electrode was found to significantly shift to the positive direction by 0.27 V (or 0.15 V), compared to the case with a chemical vapor deposited (CVD) Si electrode. On the contrary, the V<sub>fb</sub> of NiSi/HfO<sub>2</sub> with a PVD Si electrode slightly shifts to the negative direction from that with a CVD Si electrode (~0.05 V). Further, La is incorporated into HfO<sub>2</sub> to enhance the V<sub>fb</sub> modulation of Ni<sub>X</sub>Si gates with a PVD Si gate to near the conduction band edge of Si (~4.0 eV). We believe that the V<sub>fb</sub> shift of Ni<sub>X</sub>Si/HfO<sub>2</sub> is attributed to the release of Fermi-level pinning at the interface between the Si gate electrode and HfO<sub>2</sub>, arising from the different Si electrode formation process.
IEEE Transactions on Electron Devices 09/2008; · 2.32 Impact Factor
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ABSTRACT: For the first time, after considering the thermodynamic properties (evaluated by the molar Gibbs energy of oxide formation, Delta<sub>Oxide</sub>G) and the electronegativity (chi) for both the dopants (via ion implantation, thin capping layer or co-deposition) and host materials in the gate stack, a practical model to understand the effective work function (EWF) modulation induced by various dopants is proposed. It is found that the dopant oxide will determine the EWF if the Delta<sub>Oxide</sub>G of dopant (Delta<sub>Ox-dop</sub>G) is more negative than that of host gate oxide (Delta<sub>Ox-host</sub>G). Or else, chi difference between dopants and host materials will play a more critical role for determining the EWF. This model can serve as a guideline for understanding the EWF modulation by various dopants and to select appropriate gate stack materials for the gate-first technology.
VLSI Technology, 2008 Symposium on; 07/2008
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S.Z. Chang,
T.Y. Hoffmann,
H.Y. Yu,
M. Aoulaiche,
E. Rohr,
C. Adelmann,
B. Kaczer,
A. Delabie,
P. Favia,
S. Van Elshocht,
S. Kubicek,
T. Scharm,
T. Witters,
L.A. Ragnarsson, X.P. Wang,
H.J. Cho,
M. Mueller,
T. Chiarella,
P. Absil,
S. Biesemans
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ABSTRACT: This paper provides a comprehensive study of the abnormal PBTI behaviors recently observed in La/Dy-capped high-k films in low-V<sub>T</sub> nMOSFETs. We found that process details in thermal budget (or dielectric intermixing) and oxygen content of the metal trigger the onset of these abnormalities. The DeltaV<sub>T</sub> relaxation during the PBTI recovery period induced by bulk trapping/de-trapping is believed to be oxygen vacancies related, and can be suppressed either by reducing dielectric intermixing with lower laser anneal powers (La above or below HK), or by increasing the oxygen concentration, i.e., TaCNO metal electrode instead of TaCN (La above HK). Putting La below HK can result in a similar V<sub>T</sub> tune-ability with less thermal budget for intermixing with the IL (with superior PBTI), without loss of current drive-ability. We propose Ta<sub>2</sub>C/HK/LaO/IL + LLP anneals as an optimum nFETs stack configuration for practical CMOS integration.
VLSI Technology, 2008 Symposium on; 07/2008
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ABSTRACT: Powdery mildew (caused by Erysiphe graminis) and yellow rust (caused by Puccinia striiformis) are the two most serious wheat diseases found in China. Rye chromosomes, carrying genes for resistance to these diseases, were introduced into common wheat in two generations using chromosome engineering and anther culture. The F1 hybrids from a cross involving a hexaploid triticale (×Triticosecale Wittmack) בChinese Spring’ nulli-tetrasomic N6DT6A wheat aneuploid line were anther cultured and doubled-haploid plants were regenerated. Using genomic in situ hybridization, C-banding and biochemical marker analyses, one of the anther-cultured lines (ZH-1)studied in detail, proved to be a doubled-haploid with one rye chromosome pair added (1R) and a homozygous 6R/6D substitution (2n= 44). The line was tested for expression of disease resistance and found to be highly resistant to powdery mildew and moderately resistant to yellow rust.
Plant Breeding 06/2008; 120(1):39 - 42. · 1.60 Impact Factor
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S.Z. Chang,
H.Y. Yu,
C. Adelmann,
A. Delabie, X.P. Wang,
S. Van Elshocht,
A. Akheyar,
L. Nyns,
J. Swerts,
M. Aoulaiche,
C. Kerner,
P. Absil,
T.Y. Hoffmann,
S. Biesemans
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ABSTRACT: In this letter, we report that by employing the La<sub>2</sub>O<sub>3</sub>/SiO<sub>x</sub> interfacial layer between HfLaO (La = 10%) high- and Si channel, the Ta<sub>2</sub>C metal-gated n-MOSFETs V<sub>T</sub> can be significantly reduced by ~350 mV to 0.2 V, satisfying the low-Vy device requirement. The resultant n-MOSFETs also exhibit an ultrathin equivalent oxide thickness (~1.18 nm) with a low gate leakage (J<sub>G</sub> = 10 mA/cm<sup>2</sup> at 1.1 V), good drive performance (I<sub>on</sub> = 900 muA/mum at I<sub>soff</sub> = 70 nA/mum), and acceptable positive-bias-temperature-instability reliability.
IEEE Electron Device Letters 06/2008; · 2.85 Impact Factor
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X.P. Wang,
M.-F. Li,
H.Y. Yu,
J.J. Yang,
J.D. Chen,
C.X. Zhu,
A.Y. Du,
W.Y. Loh,
S. Biesemans,
A. Chin,
G.Q. Lo,
D.-L. Kwong
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ABSTRACT: For the first time, we demonstrate experimentally that using HfLaO high- kappa gate dielectric and vertical stacks of TaN/Ru metal layers, dual metal gates with continuously tunable work function over a very wide range from 3.9 to 5.2 eV, can be achieved after 1000 degC annealing required by a conventional CMOS source/drain activation process. The wide tunability of work function for this bilayer metal structure is attributed to metal interdiffusion during annealing and the release of Fermi level pinning between metal gates (Ru and TaN) and HfLaO. Moreover, this change is thermally stable and unaffected by a subsequent high temperature process.
IEEE Electron Device Letters 02/2008; · 2.85 Impact Factor
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X.P. Wang,
H.Y. Yu,
M.-F. Li,
C.X. Zhu,
S. Biesemans,
A. Chin,
Y.Y. Sun,
Y.P. Feng,
A. Lim,
Yee-Chia Yeo,
Wei Yip Loh,
G.Q. Lo,
Dim-Lee Kwong
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ABSTRACT: For the first time, we demonstrate experimentally that by using HfLaO high-kappa gate dielectric, the flat-band voltage (V<sub>fb</sub>) and the threshold voltage (Vth) of metal-electrode-gated MOS devices can be tuned effectively in a wide range (wider than that from the Si-conduction band edge to the Si-valence band edge) after a 1000-degC annealing required by a conventional CMOS source/drain activation process. As prototype examples shown in this letter, TaN gate with effective work function Phi<sub>m,eff</sub>~3.9-4.2 eV and Pt gate with Phi<sub>m,</sub>eff~5.5 eV are reported. A specific model based on the interfacial dipole between the metal gate and the HfLaO is proposed to interpret the results. This provides an additionally practical guideline for choosing the appropriate gate stacks and dielectric to meet the requirements of future CMOS devices
IEEE Electron Device Letters 05/2007; · 2.85 Impact Factor
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C.H. Wu,
B.F. Hung,
A. Chin,
S.J. Wang, X.P. Wang,
M.-F. Li,
C. Zhu,
F.Y. Yen,
Y.T. Hou,
Y. Jin,
H.J. Tao,
S.C. Chen,
M.S. Liang
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ABSTRACT: We report a novel 1000 degC stable HfLaON p-MOSFET with Ir<sub>3 </sub>Si gate. Low leakage current of 1.8times10<sup>-5</sup> A/cm<sup>2</sup> at 1 V above flat-band voltage, good effective work function of 5.08 eV, and high mobility of 84 cm<sup>2</sup>/Vmiddots are simultaneously obtained at 1.6 nm equivalent oxide thickness. This gate-first p-MOSFET process with self-aligned ion implant and 1000 degC rapid thermal annealing is fully compatible to current very large scale integration fabrication lines
IEEE Electron Device Letters 05/2007; · 2.85 Impact Factor
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C.H. Wu,
B.F. Hung,
A. Chin,
S.J. Wang,
W.J. Chen, X.P. Wang,
M.-F. Li,
C. Zhu,
Y. Jin,
H.J. Tao,
S.C. Chen,
M.S. Liang
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ABSTRACT: The authors report novel 1000degC-stable [Ir<sub>3</sub>Si-TaN]/HfLaON CMOS for the first time, where the self-aligned and gate-first process are full compatible to current VLSI. Good Phi<sub>m-eff</sub> of 5.08 and 4.24 eV, low V<sub>t</sub> of -0.10 and 0.18 V, high mobility of 84 and 217 cm<sup>2</sup>/Vs at 1.6 nm EOT, and small 85degC BTI <20 mV (10 MV/cm for 1 hr) are measured
Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
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C H Wu,
B F Hung,
Albert Chin,
S J Wang, X P Wang,
M.-F Li,
C Zhu,
F Y Yen,
Y T Hou,
Y Jin,
H J Tao,
S C Chen,
M S Liang
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ABSTRACT: We report a novel 1000 • C stable HfLaON p-MOSFET with Ir 3 Si gate. Low leakage current of 1.8 × 10 −5 A/cm 2 at 1 V above flat-band voltage, good effective work function of 5.08 eV, and high mobility of 84 cm 2 /V · s are si-multaneously obtained at 1.6 nm equivalent oxide thickness. This gate-first p-MOSFET process with self-aligned ion implant and 1000 • C rapid thermal annealing is fully compatible to current very large scale integration fabrication lines.
01/2007; 28.
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ABSTRACT: Five wheat-triticale doubled haploid (DH) lines— M08, V209, DH220-14-2, DH696-3-4 and M16 —derived from anther culture of F1s resulting from crosses involving hexaploid or octoploid triticale × hexaploid wheat, were characterized by cytological and biochemical markers. Cytological evidence from genomic in situ hybridization and C-banding indicated that DH lines M08 and V209 (2n= 42) each contained a pair of 1BL/1RS translocation chromosomes. DH220-14-2 (2n= 42) was also a translocated line with two pairs of chromosomes containing small fragments of rye. One of the translocation fragments carried the Sec-1R gene originating from the satellite region of 1RS; the origin of the other one remains unknown. DH696-3-4 (2n= 42) contained a 3D(3R) substitution. In M16 (2n= 44), three pairs of rye chromosomes, 3R, 4R and 6R, were present, 4R as an addition and 3D(3R) and 6D(6R) as substitutions. Biochemical, isozyme and storage protein markers confirmed the cytological conclusions. The advantages of transferring alien chromosomes or chromosome fragments into wheat and creating alien aneuploid lines by anther culture of hybrid F1s are discussed.
Plant Breeding 04/2006; 117(1):7 - 12. · 1.60 Impact Factor
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ABSTRACT: In this letter, we developed an improved ultrafast measurement method for threshold voltage V<sub>th</sub> measurement of MOSFETs. We demonstrate I<sub>d</sub>--V<sub>g</sub> curve measurement within 1 μs to extract the threshold voltage of MOSFET. Errors arising from MOSFET parasitics and measurement setup are analyzed quantitatatively. The ultrafast V<sub>th</sub> measurement is highly needed in the investigation of gate dielectric charge trapping effect when traps with short detrapping time constants are present. Application in charge trapping measurement on HfO<sub>2</sub> gate dielectric is demonstrated.
IEEE Electron Device Letters 02/2006; · 2.85 Impact Factor
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X.P. Wang,
Ming-Fu Li,
C. Ren,
X.F. Yu,
C. Shen,
H.H. Ma,
A. Chin,
C.X. Zhu,
Jiang Ning,
M.B. Yu,
Dim-Lee Kwong
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ABSTRACT: Using a novel HfLaO gate dielectric for nMOSFETs with different La composition, we report for the first time that TaN (or HfN) effective metal gate work function can be tuned from Si mid-gap to the conduction band to fit the requirement of nMOSFETs. This is explained by the change of interface states and Fermi pinning level by adding La into HfO<sub>2</sub>. The superior performances of the nMOSFETs compared with those using pure HfO<sub>2</sub> gate dielectric are also reported, in terms of higher crystallization temperature and higher drive current I<sub>d</sub> without sacrifice of very low gate leakage current, i.e. 5-6 orders reduction compared with SiO<sub>2</sub> at the same equivalent oxide thickness of ∼1.2-1.8 nm.
IEEE Electron Device Letters 02/2006; · 2.85 Impact Factor
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ABSTRACT: We demonstrate a program-erasable metal-insulator-silicon capacitor with a dielectric structure of SiO2/HfO2–Al2O3 nanolaminate (HAN)/Al2O3. The memory capacitor exhibits a high capacitance density of 4.5 fF/μm2, a large memory window of 1.45 V in the case of +12 V program/−12 V erase for 5 ms, nearly symmetrical positive and negative flatband voltages under the program/erase operations with the same magnitudes of voltage and time, and no erase saturation. This is attributed to the fact that the introduction of atomic-layer-deposited high-dielectric-constant HAN/Al2O3 layers increases the electric field across the tunnel oxide and reduces that across the blocking layer, hence, preventing effectively Fowler-Nordheim tunneling current through the blocking layer. Additionally, we find that the HAN is a promising charge storage layer with sufficient trapping centers for electrons and holes.
Applied Physics Letters 01/2006; 88(4):042905-042905-3. · 3.84 Impact Factor
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C. Ren,
D. S. H. Chan, X. P. Wang,
B. B. Faizhal,
M.-F. Li,
Y.-C. Yeo,
A. D. Trigg,
A. Agarwal,
N. Balasubramanian,
J. S. Pan,
P. C. Lim,
A. C. H. Huan,
D.-L. Kwong
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ABSTRACT: Lanthanide-incorporated tantalum nitride (TaN) is studied as a potential metal gate candidate for n-channel metal-oxide-semiconductor field-effect transistors (n-MOSFETs). Lanthanides such as terbium (Tb), erbium (Er), and ytterbium (Yb) are introduced into TaN to form Ta1−xTbxNy, Ta1−xErxNy, and Ta1−xYbxNy metal gates, respectively, on SiO2 dielectric. The resistivity, crystallinity, film composition, and work function of Ta1−xTbxNy, Ta1−xErxNy, and Ta1−xYbxNy films were investigated at different post-metal-anneal temperatures and for different lanthanide concentrations. It was found that the work function of lanthanide-incorporated TaN can be effectively tuned by increasing the concentration of lanthanide. Work functions of about 4.2–4.3 eV can be achieved even after a 1000 °C rapid thermal anneal, making lanthanide-incorporated TaN a promising metal gate candidate for n-MOSFETs. The enhanced nitrogen concentration and the possible presence of lanthanide-N or Ta-N-lanthanide compounds in lanthanide-incorporated TaN film could be responsible for its chemical-thermal stability on SiO2.
Applied Physics Letters 08/2005; 87(7):073506-073506-3. · 3.84 Impact Factor
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J.F. Kang,
H.Y. Yu,
C. Ren, X.P. Wang,
M.-F. Li,
D.S.H. Chan,
Y.-C. Yeo,
N. Sa,
H. Yang,
X.Y. Liu,
R.Q. Han,
D.-L. Kwong
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ABSTRACT: By using a high-temperature gate-first process, HfN--HfO<sub>2</sub>-gated nMOSFET with 0.95-nm equivalent oxide thickness (EOT) was fabricated. The excellent device characteristics such as the sub-1-nm EOT, high electron effective mobility (peak value ∼232 cm<sup>2</sup>/V·s) and robust electrical stability under a positive constant voltage stress were achieved. These improved device performances achieved in the sub-1-nm HfN--HfO<sub>2</sub>-gated nMOSFETs could be attributed to the low interfacial and bulk traps charge density of HfO<sub>2</sub> layer due to the 950°C high-temperature source/drain activation annealing process after deposition of the HfN--HfO<sub>2</sub> gate stack.
IEEE Electron Device Letters 05/2005; · 2.85 Impact Factor
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C. Ren,
H.Y. Yu, X.P. Wang,
H.H.H. Ma,
D.S.H. Chan,
M.-F. Li,
Yee-Chia Yeo,
C.H. Tung,
N. Balasubramanian,
A.C.H. Huan,
J.S. Pan,
D.-L. Kwong
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ABSTRACT: In this letter, we study Terbium (Tb)-incorporated TaN (TaTb<sub>x</sub>N) as a thermally robust N-type metal gate electrode for the first time. The work function of the Ta<sub>0.94</sub>Tb<sub>0.06</sub>N<sub>y</sub> metal gate is determined to be ∼4.23 eV after rapid thermal anneal at 1000°C for 30 s, and can be further tuned by varying the Tb concentration. Moreover, the TaTb<sub>x</sub>N-SiO<sub>2</sub> gate stack exhibits excellent thermal stability up to 1000°C with no degradation to the equivalent oxide thickness, gate leakage, and time-dependent dielectric breakdown (TDDB) characteristics. These results suggest that Tb-incorporated TaN (TaTb<sub>x</sub>N) could be a promising metal gate candidate for n-MOSFET in a dual-metal gate Si CMOS process.
IEEE Electron Device Letters 03/2005; · 2.85 Impact Factor
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ABSTRACT: In this letter, we report on a physical model to explain the frequency dependence of dynamic charge trapping in metal-oxide-semiconductor (MOS) transistors with ultrathin HfO2 gate dielectrics. For transistors operating in a complementary MOS inverter circuit with a given gate voltage amplitude, we observed a reduction of charge trapping when the stress frequency is increased. This can be explained by the traps in the high-k HfO2 dielectric have the property of negative-U centers. One trap can capture two electrons sequentially, and the trap energy is reduced as a result of lattice relaxation. Results of calculation using the model show excellent agreement with all experiment data.
Applied Physics Letters 02/2005; 86(9):093510-093510-3. · 3.84 Impact Factor
