Neil Steiner

University of Southern California, Los Angeles, California, United States

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Publications (17)1.9 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: This work presents an open-source bit stream generation tool for Torc. Bit stream generation has traditionally been the single part of the FPGA design flow that could not be openly reproduced, but our novel approach enables this without reverse-engineering or violating End-User License Agreement terms. We begin by creating a library of & micro-bit streams & which constitute a collection of primitives at a granularity of our choosing. These primitives can then be combined to create larger designs, or portions thereof, with simple merging operations. Our effort is motivated by a desire to resume earlier work on embedded bit stream generation and autonomous hardware. This is not feasible with Xilinx bitgen because there is no reasonable way to run an x86 binary with complex library and data dependencies on most embedded systems. Initial support is limited to the Virtex5, but we intend to extend this to other Xilinx architectures. We are able to support nearly all routing resources in the device, as well as the most common logic resources.
    Proceedings of the 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines; 04/2013
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    ABSTRACT: Designing hardware cores for FPGAs can quickly become a complicated task, difficult even for experienced engineers. With the addition of more sophisticated development tools and maturing high-level language-to-gates techniques, designs can be rapidly assembled; however, when the design is evaluated on the FPGA, the performance may not be what was expected. Therefore, an engineer may need to augment the design to include performance monitors to better understand the bottlenecks in the system or to aid in the debugging of the design. Unfortunately, identifying what to monitor and adding the infrastructure to retrieve the monitored data can be a challenging and time-consuming task. Our work alleviates this effort. We present the Hardware Performance Monitoring Infrastructure (HwPMI), which includes a collection of software tools and hardware cores that can be used to profile the current design, recommend and insert performance monitors directly into the HDL or netlist, and retrieve the monitored data with minimal invasiveness to the design. Three applications are used to demonstrate and evaluate HwPMI’s capabilities. The results are highly encouraging as the infrastructure adds numerous capabilities while requiring minimal effort by the designer and low resource overhead to the existing design.
    International Journal of Reconfigurable Computing 01/2012; 2012.
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    ABSTRACT: We present and describe Torc - (Tools for Open Reconfigurable Computing) - an open-source infrastructure and tool set, provided entirely as C++ source code and available at http://torc.isi.edu. Torc is suitable for custom research applications, for CAD tool development, and for architecture exploration. The Torc infrastructure can (1) read, write, and manipulate generic netlists - currently EDIF, (2) read, write, and manipulate physical netlists - currently XDL, and indirectly NCD, (3) provide exhaustive wiring and logic information for commercial devices, and (4) read, write, and manipulate bitstream packets (but not configuration frame contents). Torc furthermore provides routing and unpacking tools for full or partial designs, soon to be augmented with BLIF support, and with packing and placing tools. The architectural data for Xilinx devices is generated from non-proprietary XDLRC files, and currently supports 140 devices in 11 families: Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex4, Virtex5, Virtex6, Virtex6L, Spartan3E, Spartan6, and Spartan6L. We believe that Altera architectures and designs could be similarly supported if the necessary data were available, and we have successfully used Torc internally with custom architectures.
    Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, FPGA 2011, Monterey, California, USA, February 27, March 1, 2011; 01/2011
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    ABSTRACT: Iris recognition is one of the most accurate biometric methods in use today. However, the iris recognition algorithms are currently implemented on general purpose sequential processing systems, such as generic central processing units (CPUs). In this work, we present a more direct and parallel processing alternative using field-programmable gate arrays (FPGAs), offering an opportunity to increase speed and potentially alter the form factor of the resulting system. Within the means of this project, the most time-consuming operations of a modern iris recognition algorithm are deconstructed and directly parallelized. In particular, portions of iris segmentation, template creation, and template matching are parallelized on an FPGA-based system, with a demonstrated speedup of 9.6, 324, and 19 times, respectively, when compared to a state-of-the-art CPU-based version. Furthermore, the parallel algorithm on our FPGA also greatly outperforms our calculated theoretical best Intel CPU design. Finally, on a state-of-the-art FPGA, we conclude that a full implementation of a very fast iris recognition algorithm is more than feasible, providing a potential small form-factor solution.
    IEEE Transactions on Information Forensics and Security 01/2010; · 1.90 Impact Factor
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    N. Steiner, P. Athanas
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    ABSTRACT: Autonomous capability in space systems is rapidly becoming a necessity for continued research and exploration. While these systems have traditionally behaved as passive observers, their remoteness and unique access to unexplored environments will likely result in future systems that behave more like active agents employed on our behalf. We may still determine the larger mission goals and priorities, but the systems themselves will be better able to direct their own movement, schedule, and operation. Autonomous control of computational hardware is one of the capabilities that is becoming more desirable. We describe and demonstrate the infrastructure necessary for a computing system to autonomously change its hardware while in operation, without requiring outside intervention. The system absorbs much of its complexity into itself, and assumes responsibility for its own resources and operation. This allows it to present a simpler interface to its environment, and to autonomously respond to changes within itself or its environment. Our demonstration system works internally with circuit netlists, that it dynamically parses, places, routes, configures, connects, and implements within itself-at the finest granularity available-while continuing to run. It models itself and its resource usage, and keeps the model tightly synchronized with the changes that it undergoes, to ensure proper behavior. The system is also able to dynamically avoid resources that have been reserved or masked out because of defects or damage.
    Aerospace conference, 2009 IEEE; 04/2009
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    Neil Steiner, Peter Athanas
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    ABSTRACT: An autonomous computing system is a system that func- tions with a large degree of independence, and assumes a large amount of responsibility for its own resources and op- eration. As a counterpart to ongoing research in the software domain, this work proposes a forward-looking roadmap for systems that are able to autonomously modify their hard- ware, and considers what properties such systems require. Of particular interest is the possibility of shifting much of the associated complexity into the systems themselves. This results in simpler interfaces to the outside world, and sys- tems that are able to respond to changes in themselves or their environments with little or no outside intervention.
    Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2007, Las Vegas, Nevada, USA, June 25-28, 2007; 01/2007
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    Neil Steiner, Peter M. Athanas
    Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2007, Las Vegas, Nevada, USA, June 25-28, 2007; 01/2007
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    Neil Steiner, Peter M. Athanas
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    ABSTRACT: As computational devices continue to advance, there are reasons to examine their foundations a little more deeply, and to ask whether there may not be something more to be found. The fundamental manner in which hardware and software interact is poorly understood, and yet there is little indication in the literature that this is being discussed or ex- plored. In spite of our technological achievements, we are at a loss to precisely define the boundaries between hard- ware and software, and to describe the nature of their in- terface. This paper aims to raise some of the major issues and questions, to propose a hardware-information duality, and to suggest directions in which further research might be pursued.
    19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA; 01/2005
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    N. Steiner, P. Athanas
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    ABSTRACT: This paper presents ADB, an alternate wire database, suitable for routing, tracing, and browsing in Xilinx Virtex, Virtex-E, Virtex-II, and Virtex-II Pro FPGAs. While mainstream design flows and place-and-route tools make good use of available routing resources, they often do so at the cost of comparatively large processing times. An alternative scheme is to modify or generate configuration bitstreams directly, in order to achieve more dynamic designs and to reduce processing times and memory footprints. ADB includes a complete set of compact wire databases for the indicated families, and can generate the necessary bitstream configurations with the help of JBits or an independent bitstream interface. These wire databases can also be used in standalone mode to facilitate routing research in situations where real device data might not normally be available.
    Field-Programmable Custom Computing Machines, 2004. FCCM 2004. 12th Annual IEEE Symposium on; 05/2004
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    ABSTRACT: This paper introduces JHDLBits, the integration of two promi- nent FPGA design tools: JHDL and JBits. JHDLBits oers the low-level access and control provided by JBits with the high-level structural cir- cuit design of JHDL. Furthermore, the JHDLBits flow provides greater control of resource manipulation, placement, and routing, and gives re- searchers a "sandbox" to explore advanced interactions with FPGA bit- streams. This paper presents the overall architecture of the open-source JHDLBits project. Details are provided on how the core components - JHDL, JBits3 for Virtex-II, and the ADB connectivity database - are linked together to provide a cohesive design environment.
    Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings; 01/2004
  • Walling Cyre, Cameron Patterson, Neil Joseph Steiner
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    ABSTRACT: Modern FPGAs contain routing resources easily exceeding millions of wires. While mainstream design flows and place-and-route tools make very good use of these routing resources, they do so at the cost of very significant processing time. A well established alternative scheme is to modify or generate configuration bitstreams directly, resulting in more dynamic designs and shorter processing times. This thesis introduces a complete set of alternate wire databases for Xilinx Virtex, Virtex-E, and Virtex-II FPGAs, suitable for standalone use or as an addition to the JBits API. The databases can be used to route or trace through any device in these families, and can generate the necessary bitstream configurations with the help of JBits or an independent bitstream interface.
    10/2002;
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    Neil Steiner, Peter Athanas
    [Show abstract] [Hide abstract]
    ABSTRACT: We demonstrate and describe the infrastructure neces-sary for a computing system to autonomously change its hardware while in operation, without requiring outside in-tervention. The system absorbs much of its complexity into itself, and assumes responsibility for its own resources and operation. This allows it to present a simpler interface to its environment, and to autonomously respond to changes within itself or its environment. The demonstration system works internally with mapped netlists, that it dynamically parses, places, routes, config-ures, connects, and implements within itself—at the finest granularity available—while continuing to run. This sys-tem does not depend upon any of the Xilinx implementation tools. It models itself and its resource usage, and keeps the model tightly synchronized with the changes that it under-goes, to ensure proper behavior. The system is also able to dynamically avoid resources that have been masked out, thus making defective devices commercially viable. This ca-pability becomes critical with shrinking feature sizes, where the yield of perfect devices drops to zero.
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    Neil Joseph Steiner
    [Show abstract] [Hide abstract]
    ABSTRACT: Modern FPGAs contain routing resources easily exceeding millions of wires. While mainstreamdesign flows and place-and-route tools make very good use of these routing resources, they do so atthe cost of very significant processing time. A well established alternative scheme is to modify orgenerate configuration bitstreams directly, resulting in more dynamic designs and shorter processingtimes. This thesis introduces a complete set of alternate wire databases for Xilinx Virtex, Virtex-E,and...
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    Neil Joseph Steiner
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    ABSTRACT: Abstract Computer hardware and software have become very sophisticated since their respective beginings,
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    ABSTRACT: Iris recognition algorithms depend on image processing techniques for proper segmentation of the iris. In the Ridge Energy Direction (RED) iris recognition algorithm, the initial step in the segmentation process searches for the pupil by thresholding and using binary morphology functions to rectify artifacts obfuscating the pupil. These functions take substantial processing time in software on the order of a few hundred million operations. Alternatively, a hardware version of the binary morphology functions is implemented to assist in the segmentation process. The hardware binary morphology functions have negligible hardware footprint and power consumption while achieving speed up of 200 times compared to the original software functions.
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    ABSTRACT: Configurable computing researchers are often sidetracked by tool and infrastructure needs while pursuing unique and novel work, and frequently resort to simplified device models for lack of real architectural data. To address these issues, we present and describe Torc, an open-source C++ infrastructure and tool set for reconfigurable computing, suitable for custom research applications, for CAD tool devel-opment, and for architecture exploration. The Torc infrastructure can read, write, and manipulate EDIF, BLIF, and XDL netlists, as well as Xilinx bitstream packets (without however understanding configuration frame internals). The Torc tools include placing and routing for full or partial designs, along with additional capabilities to facilitate design manipulation and analysis. In support of these capabilities, Torc provides exhaustive wiring and logic information for all major Xilinx devices, derived from non-proprietary sources. We believe that Altera architectures and designs could be similarly supported if the necessary data were available, and we have successfully used Torc internally with custom architectures. We present some examples of capabilities built with Torc, including an EDIF obfuscator, an XDL sub-circuit extractor, and a third-party partial reconfiguration tool. Torc is open-source software and is available at http://torc.isi.edu.
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    Neil Joseph Steiner

Publication Stats

90 Citations
1.90 Total Impact Points

Institutions

  • 2009–2012
    • University of Southern California
      • • Information Sciences Institute
      • • Spatial Sciences Institute
      Los Angeles, California, United States
  • 2010
    • United States Naval Academy
      • Department of Electrical and Computer Engineering
      Annapolis, Maryland, United States
  • 2004–2005
    • Virginia Polytechnic Institute and State University
      • Department of Electrical and Computer Engineering
      Blacksburg, Virginia, United States