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ABSTRACT: We propose a floorplan-aware complexity reduction methodology for digital filters. Conventional methodologies for complexity reduction use logic-centric approaches focusing on the total number of adders. Therefore, there is a need to consider interconnects to reduce communication costs while synthesizing reduced-complexity filters. In this paper, we integrate high-level synthesis and floorplan to obtain improvement in both computational complexity and interconnect delay. In our experiments, we could achieve 15% improvement in critical-path delay over conventional methodologies.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 03/2006; · 1.22 Impact Factor
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ABSTRACT: We present a graph theoretical methodology that reduces the implementation complexity of the multiplication of a constant vector and a scalar. The complexity of implementation is defined as the required amount of computations like additions. The proposed approach is called minimally redundant parallel (MRP) optimization and is mainly presented in a finite impulse response (FIR) filtering framework to obtain a low-complexity multiplierless implementation. The key idea is to expand the design space using shift inclusive differential coefficients (SIDCs) together with computation reordering using a graph theoretic approach to obtain maximal computation sharing. The problem is formulated using a graph in which vertices and edges represent coefficients and computational cost (number of resources). The multiplierless solution is obtained by solving a set cover problem on the vertices in the graph. A simple polynomial run time algorithm based on a greedy approach is presented. The proposed approach is compared with common-subexpression elimination to show slightly better results and is combined with it for further reduction of complexity. Simulation results show that 50-60% complexity reduction is achieved by only applying the MRP algorithm, and 70% complexity reduction is obtainable by combining it with common-subexpression elimination under a delay constraint of two or three.
IEEE Transactions on Signal Processing 07/2004; · 2.63 Impact Factor
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ABSTRACT: This paper presents a programmable digital finite-impulse response (FIR) filter for high-performance and low-power applications. The architecture is based on a computation sharing multiplier (CSHM) which specifically targets computation re-use in vector-scalar products and can be effectively used in the low-complexity programmable FIR filter design. Efficient circuit-level techniques, namely a new carry-select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. A 10-tap programmable FIR filter was implemented and fabricated in CMOS 0.25-μm technology based on the proposed architectural and circuit-level techniques. The chip's core contains approximately 130 K transistors and occupies 9.93 mm<sup>2</sup> area.
IEEE Journal of Solid-State Circuits 03/2004; · 3.23 Impact Factor
