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ABSTRACT: Accurate performance modeling is essential for its usage in a circuit synthesis flow. Only a small fraction of the entire design space is occupied by designs with meaningful behavior and performance. In this work, we have focussed on modeling these feasible regions accurately in contrast with modeling the entire design space. Macromodels for the feasible regions were built hierarchically until the desired accuracy was achieved. An accuracy driven synthesis methodology is proposed to guide the identification of the feasible regions and dynamically enhance the performance of the macromodels. Dynamic performance modeling ensures true convergence of our synthesis approach as opposed to existing static macromodel based techniques. We applied the proposed methodology for modeling and synthesis of several analog and RF circuits and the results demonstrate that our approach yields highly accurate design solutions in a much smaller time compared to simulation based approaches.
Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on; 12/2005
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ABSTRACT: We propose a methodology for sizing radio-frequency circuits. Techniques for including layout information during circuit sizing have been presented. The aim of the proposed technique is to obtain parasitic closure at the post-layout validation stage. A two-step approach is adopted for achieving this goal. In the first step, the interconnect parasitic bounds are estimated. In the second step, the parasitic bounds are used to identify the worst case parasitics and the circuit is resized in presence of these parasitics. The proposed approach unlike existing layout-inclusive approaches achieves parasitic closure while not restricting the flexibility and quality of the physical layout. This methodology was applied on RF circuits like low noise amplifiers and the results demonstrate that our technique helps in obtaining robust parasitic aware design solutions.
Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on; 11/2005
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ABSTRACT: This paper presents a new method to perform efficient analog circuit synthesis by using accurate multiparameter sensitivity analysis based on element-coefficient diagrams (ECDs). An ECD is the cancellation-free and per-coefficient term generation version of determinant decision diagrams (DDDs). The techniques based on DDD are the fastest symbolic analysis algorithms reported so far in literature. The symbolic multiparameter sensitivity equations obtained from ECDs can be evaluated so as to tune the parameters in analog synthesis process efficiently. The proposed methodology has been applied for the synthesis of a two stage opamp circuit. The experimental results demonstrate that the speed and convergence of analog synthesis are improved significantly.
VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on; 06/2005
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ABSTRACT: Accounting for the effects of inductive, resistive as well as capacitive parasitics of interconnects and on-chip inductors is essential to the success of parasitic-aware RF circuit synthesis at high frequencies. This paper presents an approach for RF circuit synthesis, based on fast procedural layout generation and extraction of all parasitics using multiple extractors. While the parasitic capacitances are obtained using standard rule-based techniques, parasitic resistances and inductances are computed using a fast, yet accurate quasi-static inductance extraction method. Both self and mutual inductances and resistances of inductors and interconnects, which play a significant role at high frequencies, are accounted in the process. A simulated-annealing based optimization algorithm controls design space exploration. Synthesis results show that the proposed methodology yields designs that are more realistic and accurate compared to approaches that ignore resistive and inductive parasitics of interconnects.
Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on; 08/2004
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ABSTRACT: This paper presents efficient and accurate techniques for modeling parasitic capacitances in analog CMOS circuits. A layout aware synthesis flow using these parasitic models has been proposed. The fast parasitic estimation process replaces the time consuming steps of layout generation and extraction during synthesis. Results indicate that these models are extremely fast and accurate.
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings; 03/2004
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ABSTRACT: We present a new methodology for fast analog circuit synthesis, based on the use of parameterized layout generators and symbolic performance models (SPMs) in the synthesis loop. Fast layout generation is achieved by using efficient parameterized procedural layout generators. Fast performance estimation is achieved by using pre-compiled SPMs, stored as efficient DDD-like structures called element coefficient diagrams. Techniques have been developed to include layout geometry effects in the SPMs. The accuracy and efficiency of the parasitic inclusion technique as well as the proposed methodology have been demonstrated by comparisons to traditional synthesis methods. The proposed methodology is used for the synthesis of opamps and filters and is demonstrated to achieve effective performance closure.
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings; 03/2004
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Design Automation Conference, 2004. Proceedings. 41st; 02/2004
