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[hide abstract]
ABSTRACT: AC electrochemical etching in diluted potassium hydroxide (KOH) solution was optimized to fabricate tungsten (W) nanotips
with a controllable sharpness and aspect ratio using an additional lift-up step. The final tip profile was dependent on the
extent of interaction between the KOH solution and the side of the W surface, and effective bubble shielding effects near
the apex region during the lift-up. Lateral etching rate along the W material was affected by parameters such as electrolyte–cathode
positioning, etching voltage, and electrode size that influenced the flow or replenishment rate of
ions to the W surface submerged in the solution and at the meniscus region. With the lift-up step, the dense layer of bubbles
that formed during etching could provide a good shield in minimizing the etch-back effects on the tip apex. Combining the
above investigated effects, sharp nanotips with the required aspect ratio could be achieved with the enhanced lateral etching
and the protective shield of bubbles.
Journal of The Electrochemical Society. 12/2009; 157(1):E6-E11.
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ABSTRACT: Selection of optimized electron beam parameters for in-line monitoring is necessary to eliminate false signals. Application of electron beam to detect electrical defects, particularly leakages, for static random access memory (SRAM) cells poses a great challenge as it requires current measurement tool with nanometer resolution to complement it. By correlating the brightness intensity or the gray-level value to the measured current values, we have shown that conductive atomic force microscopy (C-AFM) can overcome this obstacle and can be used to verify the validity of the voltage contrast (VC) captured by HMI eScan3xx Ebeam inspection tool.
Physical and Failure Analysis of Integrated Circuits, 2008. IPFA 2008. 15th International Symposium on the; 08/2008
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ABSTRACT: With the shrinkage of the transistor dimensions, the spacing between the structures become smaller and smaller. However due to the intrinsic characteristic of the CMOS device, the reduction of the operating voltage is limited. The electrical field between different structures keeps on increasing with the shrinkage of the transistor dimensions. Furthermore, many new failure modes were observed with the scaling of semiconductor device. One of them is poly gate to contact leakage. In this paper, the mechanism of the leakage failure between poly gate and the contact in subnano CMOS technology was discussed.
Physical and Failure Analysis of Integrated Circuits, 2008. IPFA 2008. 15th International Symposium on the; 08/2008
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ABSTRACT: With the miniaturization of electronic devices, identifying the root cause of soft failures using physical failure analysis (PFA) techniques has become a more challenging task. By characterizing the electrical behavior of malfunctioned devices, nanoprobing precisely locates defects before any PFA is performed and allows for deeper understanding of the root cause of soft failure issues. Two case studies are presented to demonstrate the effectiveness of nanoprobing in investigating the root causes of soft failures.
Physical and Failure Analysis of Integrated Circuits, 2008. IPFA 2008. 15th International Symposium on the; 08/2008
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S.L. Toh,
P.K. Tan,
Y.W. Goh,
E. Hendarto,
J.L. Cai,
H. Tan,
Q.F. Wang,
Q. Deng,
J. Lam,
L.C. Hsia,
Z.H. Mai
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ABSTRACT: This paper highlights the use of a localized probing technique, nanoprobing, to reveal some of the subtle defects affecting the yield of integrated circuits in the nanometer generation nodes. The tool is equipped with the capability to isolate and characterize the exact failing transistors of the malfunctioned devices. As a result, the identification process of the failure mechanisms, and hence the root cause, can be accelerated. The electrical characterization at the transistor level also offers an appropriate guide to the required physical analysis that has to be carried out in order to ldquovisualizerdquo the defects. Based on the in-depth diagnosis of the defective site, the three case studies covered in this paper demonstrate the importance of this advanced failure-analysis methodology. For the analysis, static random-access-memory test-chips were used. With that, marginal failures or degradations relating to the ultrathin gate oxides, variations in the resistance of the implanted layers in the substrate, and abnormal passive-voltage-contrast signature were determined.
IEEE Transactions on Device and Materials Reliability 07/2008; · 1.54 Impact Factor
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H. Tan,
P.K. Tan,
E. Hendarto, S.L. Toh,
Q.F. Wang,
J.L. Cai,
Q. Deng,
T.H. Ng,
Y.W. Goh,
Z.H. Mai,
J. Lam
[show abstract]
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ABSTRACT: NiSi has replaced CoSi<sub>2</sub> as the salicide material for 65 nm technology and beyond mainly due to its low salicide resistance for the narrow line width structures. However, it may bring along unwanted salicidation, resulting in failed transistors. This paper highlights how unwanted salicidation, also known as Ni piping, is successfully identified by physical and electrical failure analysis techniques.
Physical and Failure Analysis of Integrated Circuits, 2007. IPFA 2007. 14th International Symposium on the; 08/2007
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S.L. Toh,
Z.H. Mai,
P.K. Tan,
E. Hendarto,
H. Tan,
Q.F. Wang,
J.L. Cai,
Q. Deng,
T.H. Ng,
Y.W. Goh,
J. Lam,
L.C. Hsia
[show abstract]
[hide abstract]
ABSTRACT: Nanoprobing plays a crucial role for failure analysis (FA) in the nanometer-region generation nodes by having the capability to detect the failure sites and characterize the electrical behaviour of malfunctional devices for better understanding of the failure mechanisms. It also offers a guide to the necessary physical analysis in identifying the cause of failure. This established electrical failure analysis (EFA) methodology at a localized area helps to accelerate the FA. Its application to few of the front-end issues is highlighted in the paper.
Physical and Failure Analysis of Integrated Circuits, 2007. IPFA 2007. 14th International Symposium on the; 08/2007
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C.H. Ang,
W.H. Lu,
A.K.L. Yap,
L.C. Goh,
L.N.L. Goh,
Y.K. Lim,
C.S. Chua,
L.H. Ko,
T.H.S. Tan, S.L. Toh,
L.C. Hsia
[show abstract]
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ABSTRACT: The influence of the SiN cap-layer NH<sub>3</sub> pre-treatment process on the electromigration (EM), plasma-induced damage (PID), gate oxide integrity (GOI) and BEOL defectivity has been studied. A noteworthy trade-off between EM, PID, GOI performance, and BEOL defectivity is revealed. On one hand, aggressive NH<sub>3</sub> pre-treatment process yields improved EM lifetime and PID. On the other hand, the process may provoke Cu hillock and IMD blister defects, as well as GOI yield failure if the treatment is over-aggressive. These disparate observations have been satisfactorily explained using RF plasma-induced heating mechanism in the underlying Cu and IMD. This paper also shows the need to adjust the NH<sub>3</sub> pretreatment process to meet the overall yield, reliability and manufacturability requirements.
Integrated Circuit Design and Technology, 2004. ICICDT '04. International Conference on; 02/2004
