I. Cayrefourcq

Soitec, Rhône-Alpes, France

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Publications (33)17.59 Total impact

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    ABSTRACT: Raman spectroscopy is a powerful and versatile technique for stress measurements in complex stacks of thin crystalline layers at macroscopic and microscopic scales. Using such a technique we show that thick SiGe layers epitaxially grown using graded buffer method are fully relaxed (>95%) at a macroscopic scale but exhibit a small strain modulation at a microscopic scale. For the first time we report the results of Raman micro-mapping of stress distribution in SGOI wafers produced by Smart Cut TM technology. We conclude that Smart Cut TM is a unique method to manufacture the next generation of engineered wafers that can combine strained and/or relaxed SiGe alloys, Si and Ge films, while keeping their initial strain properties at both scales. It is important to develop Raman spectroscopy tool for in-line process control in fabrication of strained Silicon On Insulator (sSOI) wafers.
    MRS Online Proceeding Library 01/2011; 809. DOI:10.1557/PROC-809-B3.1
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    ABSTRACT: Omega gate type pFETs with SiGe shell-Si core are demonstrated that show 30% mobility enhancement for (110) oriented fins and 46% mobility enhancement for (100) oriented fins compared to Si omega gate devices. Performance improvement is demonstrated because of higher mobility and inherent epitaxial strain, while the external resistance in the two SiGe and Si omega FETs is comparable. Performance can further be improved by uniaxial compressive stress.
    VLSI Technology, Systems, and Applications, 2009. VLSI-TSA '09. International Symposium on; 05/2009
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    ABSTRACT: Biaxial tensile strained substrates offer strong electron mobility enhancements resulting in large drive current gains. For short channel n-MOSFETs, however, these improvements diminish. Root causes for this performance degradation are investigated through experiments and simulations. Elastic stress relaxation arising from shallow trench isolation (STI) is found to be negligible for current state-of-the-art transistors. On the other hand, parasitic source/drain resistance seems to be responsible for the limitation of drain current gains in deeply scaled devices. This effect is even further aggravated by an increased parasitic source/drain resistance in sSOI devices compared to standard SOI.
    Ultimate Integration of Silicon, 2009. ULIS 2009. 10th International Conference on; 04/2009
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    ABSTRACT: We have performed systematic measurements of the splitting kinetics induced by H-only and He + H sequential ion implantation into relaxed Si <sub>0.8</sub> Ge <sub>0.2</sub> layers and compared them with the data obtained in Si. For H-only implants, Si splits faster than Si <sub>0.8</sub> Ge <sub>0.2</sub> . Sequential ion implantation leads to faster splitting kinetics than H-only in both materials and is faster in Si <sub>0.8</sub> Ge <sub>0.2</sub> than in Si. We have performed secondary ion mass spectrometry, Rutherford backscattering spectroscopy in channeling mode, and transmission electron microscopy analyses to elucidate the physical mechanisms involved in these splitting phenomena. The data are discussed in the framework of a simple phenomenological model in which vacancies play an important role.
    Journal of Applied Physics 01/2009; 104(11-104):113526 - 113526-5. DOI:10.1063/1.3033555 · 2.19 Impact Factor
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    ABSTRACT: Thermal stability of strained SOI fabricated by Smart Cut technique was found to be high enough for the current Si process, particularly with SiO2 protection films. The strain states, in-plane and out-of-plane lattice constants, were found not to change after annealing up to 1150 °C with SiO2 films though those of thinner sSOI without the protection film gradually changed due to strain relaxation. It was also found that 3D correction of the orientation mismatch between the Si substrate and the strained Si was essential for precise evaluation of strain states.
    Thin Solid Films 11/2008; 517(1-517):340-342. DOI:10.1016/j.tsf.2008.08.154 · 1.87 Impact Factor
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    ABSTRACT: Scalability of both unstrained and strained FDSOI CMOSFETs is explored for the first time down to 2.5 nm film thickness and 18 nm gate length with HfO<sub>2</sub>/TiN gate stack. Off-state currents in the pA/mum range are achieved for 18 nm short and 3.8nm thin MOSFETs thanks to outstanding electrostatic control: 67 mV/dec subthreshold swing and 75 mV/V DIBL. For such thin bodies, the buried oxide fringing field limitation on DIBL is experimentally evidenced and quantified for the first time. Furthermore, we demonstrate strain induced I<sub>ON</sub> gain as high as 40% on the shortest transistors. An in-depth analysis of this gain as a function of the film thickness is carried out through mobility and ballisticity extractions.
    Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
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    ABSTRACT: The current status of SOI technology using wafer bonding is reviewed and its technological positioning in CMOS scaling is discussed. While bulk CMOS technology is encountering various kinds of critical issues, SOI technology using wafer bonding provides unique solutions by virtue of its flexible material design. Mobility enhancement through strained-SOI (sSOI) or optimization of crystal orientation (HOT, DSB), dynamic threshold voltage control by back-biasing (UT-BOX SOI), capacitor-less DRAM, etc., are promising options that can bring a breakthrough and continue proper scaling. Also, circuit layer transfer technology applied to back-side illumination of CMOS imager is presented, as a technology giving linkage with future 3D-integration of LSI system.
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    ABSTRACT: Silicon-on-Insulator (SOI) is today the substrate of choice for several applications. In order to boost further circuit performance, new solutions are being explored. In particular, increasing the charge carrier mobility has been identified as a requirement for the next technology nodes. One possible option is to increase transistor channel mobility through local strain engineering via external Stressors, an approach that can be used on bulk silicon as well as standard SOI substrates. Other solutions are based on substrate engineering. The attractiveness of these solutions is largely due to their compatibility with standard CMOS integration processes and architectures and presents the advantage of being independent of transistor geometry. The two approaches can be combined to maximize transistor mobility and on-current. Among the different substrate level approaches, we will focus on three main families: (1) the effect of crystal orientation, (2) strained Si and/or SiGe layers On Insulator, and (3) monocrystalline Ge-On-Insulator substrates.
    12/2007: pages 43-72;
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    ABSTRACT: The strain state and thermal stability of strained-Si-on-insulator (sSOI) substrates fabricated by the Smart Cut\textregistered technique were precisely analyzed by X-ray diffraction reciprocal space mapping and Raman spectroscopy. It was demonstrated that the strain was well maintained even after annealing at temperatures up to 1120 °C in spite of the thickness being larger than the critical thickness. The strain reduction of only 10% was observed at 1150 °C, but the surface smoothness with the RMS roughness below 0.2 nm and high crystal quality did not change. This indicates the high applicability of sSOI to the current Si processes.
    Japanese Journal of Applied Physics 11/2007; 46(11):7294-. DOI:10.1143/JJAP.46.7294 · 1.06 Impact Factor
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    ABSTRACT: In this letter, we investigate the impact of a hybridized strain technology on the performance of FinFET-based multigate field-effect transistors (MUGFETs). The technology combines the use of supercritical strained-silicon-on-insulator (SC-SSOI) and strained contact etch stop layers (CESLs). We will show that SC-SSOI (top plane orientation ) with tensile CESL (tCESL), when used for MUGFET, leads to higher improvement in electron mobility as compared to standard SOI with tCESL. Therefore, the combination of both mobility boosters is very beneficial for n-channel MOS MUGFET. However, the impact of compressive CESL on p-channel MOS (pMOS) performance is strongly reduced and becomes even negative when used on an SC-SSOI substrate. Local strain relief of the SC-SSOI substrate is mandatory in order to achieve good pMOS device performance.
    IEEE Electron Device Letters 08/2007; DOI:10.1109/LED.2007.900174 · 3.02 Impact Factor
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    ABSTRACT: In order to continue improving strained silicon-on-insulator (sSOI) crystal quality, high-resolution defect monitoring needs to be developed and implemented for further defects reduction. The study presented in this paper evaluates and compares two techniques for revealing crystal defects in sSOI wafers produced by the Smart-Cut Technology. Two different etching techniques, based on the use of gaseous in an epitaxy reactor or of a diluted Secco wet etching solution, were compared on their ability to delineate various defects. Both techniques should provide the required defects density resolution for analysis of thin and thick strained silicon layers. For the sake of analysis and discussion, samples with a high defects density were chosen in order to simplify the quantitative comparison (within the resolution of optical microscopy). We have observed a difference in etching selectivity between the two techniques. After a statistical comparison of defects delineated by the two techniques (in terms of threading dislocations, areal densities, and planar defect linear densities), we have demonstrated complementarities rather than a direct correlation between the and Secco etch. The etch seems quite suitable for revealing threading dislocations through etch pits and shows a higher sensitivity for pit delineation compared to Secco (difference corresponding to a factor of 10 in defects density). Meanwhile, the Secco chemical etching appears more appropriate to highlight the planar defects (linear density between 600 and ). Moreover, a minimum etched thickness for sSOI defect revelation has been determined for both techniques (between 26 and for and between 20 and for Secco for a thick starting layer). Because the Secco etch is particularly sensitive for the delineation of various types of defects (isolated etch pits and planar defects), it is now used by us as a quality control method for SOI and sSOI. Thanks to it sSOI process improvements are tracked and current and next generations of this product evaluated.
    07/2007; 154(8):H713-H719. DOI:10.1149/1.2740032
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    ABSTRACT: For the first time, we integrated 1.9 GPa eXtra-strained silicon on insulator (XsSOI) substrates in FDSOI n and pMOSFETs with gate length (L<sub>G</sub>) and width (W) down to 25 nm. Due to the high stress levels, significant I<sub>ON</sub>-I<sub>OFF</sub> improvements were obtained not only for nMOS but also for pMOS. We compared those results with the performance of devices strained by contact etch stop layer (CESL), for different device orientations (<110> or <100>) and feature sizes (L<sub>G</sub>, W). We demonstrate that, similarly to XsSOI, a single tensile CESL can improve both n and pMOS performance, leading to I<sub>ON,n</sub>=700 muA/mum and I<sub>ON,p</sub>=430 muA/mum at I<sub>OFF</sub>=140 pA/mum, this for L<sub>G</sub><35 nm, W=50 nm and V<sub>DD</sub>=1 V along the <100> direction.
    VLSI Technology, 2007 IEEE Symposium on; 07/2007
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    ABSTRACT: This paper describes a comprehensive study of the impact of tCESL (tensile Contact Etch Stop Liner) and cCESL (compressive Contact Etch Stop Liner) on tensile metal gate MuGFET with SOI and globally strained SOI (sSOI) substrates. We have demonstrated that tCESL and cCESL can be effectively used on MuGFETs to provide performance gain. Since tCESL and cCESL affect NMOS and PMOS mobilities in the opposite directions, dual stress liner technology with high-stress cCESL is needed for optimal CMOS MuGFET performance.
    VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on; 05/2007
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    ABSTRACT: MuGFET structure improves local transistor mismatch compared to planar bulk MOSFET. This enables further SRAM cell size reduction. GIDL current is well controlled even with a mid-gap metal gate. MuGFETs have low subthreshold leakage if Lg/Wsi ratio is kept above 1.5. The advantage of MuGFET subthreshold leakage suppression is even more pronounced at higher temperatures. Furthermore MuGFETs are compatible with local strain techniques to improve carrier mobility. The aforementioned qualities, along with low manufacturing cost of single mid- bandgap metal gate, make MuGFET a good candidate to replace planar bulk MOSFET for Low-Power Applications.
    ECS Transactions 04/2007; 6(4). DOI:10.1149/1.2728842
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    ABSTRACT: To meet HP and LP circuit requirements, increasing channel mobility is required to boost transistor performance and/or reduce Vdd for lower power dissipation without performance penalty. The ultra-thin body (UTB) devices with undoped and strained channels can be used to control the SCE and reduce the sub-threshold leakage for scaling and low power dissipation. Implementing strained-silicon is not just a substrate change; strained- Si will require much more extensive work as transistor scaling continues.
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    ABSTRACT: Ion implantation is a subject of interest because it is widely used in the semiconductor industry, to modify the carrier density in a transistor channel region and to enable splitting in the wafer bonding process. In the case of SOI wafers produced by SmartCut™, the implantation of light ions creates only a small amount of damage in the materials. Thus, H-implanted Si remains crystalline and only small changes are observed in physical properties as compared to non-implanted silicon crystal. However, as energy is applied to the system, by heating for example, H-implanted Si undergoes extreme stress eventually breaking the crystal. We have investigated the changes in the Si crystal during this process using Raman spectroscopy. Examining the slight shift and enlargement of the phonon peak and applying the spatial correlation model characterized defects. We could extract a phonon correlation length L, the shorter the L value, the larger the amount of defects. Variations due to H concentration (implantation depth profile relative to the surface) were investigated by using different excitation wavelengths (probe depths of 20–500nm). Samples were also thinned by etching so that the defect density could be measured with fixed excitation energy (fixed probe depth). Finally, we draw the variation of L. All results were compared to the vacancy profiles simulated with the binary collision code IMSIL. Good agreement was obtained between the defect profiles estimated by both methods.
    Nuclear Instruments and Methods in Physics Research Section B Beam Interactions with Materials and Atoms 12/2006; 253(1):182-186. DOI:10.1016/j.nimb.2006.10.027 · 1.19 Impact Factor
  • M. Yoshimi, I. Cayrefourcq, C. Mazure
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    ABSTRACT: Current status of strained-SOI (sSOI) substrate technology is reviewed along with relevant device-level strain optimization. Smart Cut trade enables to transfer a tensile-strained Si film, grown on Si<sub>0.8</sub>Ge<sub>0.2</sub>, onto a 300mm Si wafer, with excellent thickness uniformity and preserved stress. The pile-ups (PUs) have been eliminated and the threading dislocation density has been significantly reduced. Strained-Si film can be 80nm thick, making implementation of partially-depleted (PD) structure practical. The stress endures thermal treatment up to 1100 degree C, for 2 hours. Technology directions for PMOS improvement are discussed, including combination with uniaxial stress technologies
    Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on; 11/2006
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    ABSTRACT: The fully depleted (FD) SOI MOSFET is generally considered as one of the best candidates for next CMOS technology nodes. However, new technological boosters need to be introduced in the classical FD SOI process flow to reach the very aggressive I<sub>on</sub>/I<sub>off</sub> specifications predicted by the ITRS roadmap. The use of a thin buried oxide (BOX) on FD SOI is still a controversial subject, despite recent publications that have demonstrated its interest for improvement of short channel effect (SCE) control, especially with a ground plane (GP) integration (Tsuchiya et al.). In order to improve the device performances, a strained "contact etch stop layer" (CESL) technique has been successfully demonstrated to induce strain into the channel of bulk devices (Thompson et al., 2002) as well as in ultra-thin FD SOI devices (Singh et al., 2005 and Gallon et al., 2006). However, its compatibility with the specific technological features of FD SOI devices, such as silicon film thickness (T<sub>S1</sub>) variations, BOX material and BOX thickness (T<sub>BOX</sub>), raised source/drain architecture, has yet to be clarified. In this paper, we demonstrate, by electrical and mechanical simulations, the interest of thin BOX with GP, combined with a strained liner. These simulations have then been validated by measurements, showing excellent I<sub>on</sub>/I<sub>off</sub> pMOS performances
    International SOI Conference, 2006 IEEE; 11/2006
  • Ian Cayrefourcq, Alice Boussagol, G. Celler
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    ABSTRACT: In this paper we highlight the complementarities of process-induced stress and wafer level stress (sSOI). We first present a state of the art of the various strain engineering techniques used in production for both PMOS and NMOS devices and discuss their scalability for 45nm and 32nm nodes using some mechanical modeling. In a second part, we explain how wafer level stress can be used together with process-induced stress to overcome these difficulties and insure further performance enhancement. We discuss some device data showing compatibility and additivity of process-induced and wafer level stress. Finally, we give an overview of further sSOI developments that will insure scalability beyond 32nm.
    ECS Transactions 10/2006; 3(7). DOI:10.1149/1.2355837
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    ABSTRACT: Embedded-SiGe is shown to be fully compatible with strained-SOI substrates. Despite a lack of lateral lattice mismatch between the SiGe and strained-SOI, the resulting drive current improvement from embedded-SiGe is identical for strained-SOI and standard SOI control (where a lateral lattice mismatch is present). This result isolates the vertical lattice mismatch as the source of stress generation from embedded-SiGe. The concept of a critical length of SiGe beyond the vertical Si-SiGe interface is introduced to explain the observed experimental results, and is confirmed by various SiGe epitaxial fill-height and stress relaxation experiments.
    ECS Transactions 10/2006; 3(7). DOI:10.1149/1.2355867